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authorStefan Roese <sr@denx.de>2008-01-09 10:28:20 +0100
committerStefan Roese <sr@denx.de>2008-01-09 10:28:20 +0100
commit8f24e0637ae113500d8bd60d80d57afcc0aa8bde (patch)
tree4f17b423e33303a05b883cfede86c1b42714283b /include/ppc440.h
parent1754f50b710194f886b6f2831803d8960171a14d (diff)
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ppc4xx: Change LWMON5 to not use OCM for init-ram and POST anymore
This patch configures the LWMON5 port to use d-cache as init-ram and the unused GPT0_COMP6 as POST WORD storage. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/ppc440.h')
-rw-r--r--include/ppc440.h4
1 files changed, 1 insertions, 3 deletions
diff --git a/include/ppc440.h b/include/ppc440.h
index 90e56b0..b0d16fb 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1354,8 +1354,6 @@
#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* Pin Function Control Register 1 */
#define SDR0_PFC1 0x4101
#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
@@ -1421,7 +1419,7 @@
#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
-#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
+#define GPT0_COMP6 0x00000098
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR0_USB2D0CR 0x0320