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| author | Haavard Skinnemoen <hskinnemoen@atmel.com> | 2007-06-19 15:40:01 +0200 |
|---|---|---|
| committer | Haavard Skinnemoen <hskinnemoen@atmel.com> | 2007-06-19 15:40:01 +0200 |
| commit | 448f5fea4c7dd531b69e4e60eed2a72b89b4ed6d (patch) | |
| tree | 022599b68a0e72f34f3f152f4a0056b557a06a44 /include/ppc440.h | |
| parent | f2134f8e9eb006bdcd729e89f309c07b2fa45180 (diff) | |
| parent | 5ffa76a032279bc6d3230b703eda32d13305ba13 (diff) | |
| download | u-boot-imx-448f5fea4c7dd531b69e4e60eed2a72b89b4ed6d.zip u-boot-imx-448f5fea4c7dd531b69e4e60eed2a72b89b4ed6d.tar.gz u-boot-imx-448f5fea4c7dd531b69e4e60eed2a72b89b4ed6d.tar.bz2 | |
Merge branch 'upstream'
Diffstat (limited to 'include/ppc440.h')
| -rw-r--r-- | include/ppc440.h | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/include/ppc440.h b/include/ppc440.h index bc1d7aa..07f75de 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1425,9 +1425,6 @@ /*----------------------------------------------------------------------------+ | Clock / Power-on-reset DCR's. +----------------------------------------------------------------------------*/ -#define CPR0_CFGADDR 0x00C -#define CPR0_CFGDATA 0x00D - #define CPR0_CLKUPD 0x20 #define CPR0_CLKUPD_BSY_MASK 0x80000000 #define CPR0_CLKUPD_BSY_COMPLETED 0x00000000 @@ -3314,6 +3311,23 @@ #define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0) #define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0) +/* + * All 44x except 440GP have CPR registers (indirect DCR) + */ +#if !defined(CONFIG_440GP) +#define CPR0_CFGADDR 0x00C +#define CPR0_CFGDATA 0x00D + +#define mtcpr(reg, data) do { \ + mtdcr(CPR0_CFGADDR, reg); \ + mtdcr(CPR0_CFGDATA, data); \ + } while (0) + +#define mfcpr(reg, data) do { \ + mtdcr(CPR0_CFGADDR, reg); \ + data = mfdcr(CPR0_CFGDATA); \ + } while (0) +#endif #ifndef __ASSEMBLY__ |