summaryrefslogtreecommitdiff
path: root/include/ppc405.h
diff options
context:
space:
mode:
authorStefan Roese <sr@denx.de>2008-06-02 14:57:41 +0200
committerStefan Roese <sr@denx.de>2008-06-03 20:21:53 +0200
commit36ea16f6a066ccb046e91ebce4f326b69f4c0569 (patch)
tree73d71323f1cc3303a639fce2421757855ba75db9 /include/ppc405.h
parent64852d09e06dd6db2b2db2a3c59bc2db176a54d6 (diff)
downloadu-boot-imx-36ea16f6a066ccb046e91ebce4f326b69f4c0569.zip
u-boot-imx-36ea16f6a066ccb046e91ebce4f326b69f4c0569.tar.gz
u-boot-imx-36ea16f6a066ccb046e91ebce4f326b69f4c0569.tar.bz2
ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part1
This patch removes all SDRAM related defines from the PPC4xx headers ppc405.h and ppc440.h. This is needed since now some 405 PPC's use the same SDRAM controller as 440 systems do (like 405EX and 440SP). It also introduces new defines for the equipped SDRAM controller based on which PPC variant is used. There new defines are: used on 405GR/CR/EP and some Xilinx Virtex boards. used on 440GP/GX/EP/GR. used on 440EPx/GRx. used on 405EX/r/440SP/SPe/460EX/GT. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/ppc405.h')
-rw-r--r--include/ppc405.h414
1 files changed, 0 insertions, 414 deletions
diff --git a/include/ppc405.h b/include/ppc405.h
index c994289..2231a5f 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -480,33 +480,6 @@
#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2)
#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3)
-/******************************************************************************
- * SDRAM Controller
- ******************************************************************************/
- /* values for memcfga register - indirect addressing of these regs */
-#ifndef CONFIG_405EP
- #define mem_besra 0x00 /* bus error syndrome reg a */
- #define mem_besrsa 0x04 /* bus error syndrome reg set a */
- #define mem_besrb 0x08 /* bus error syndrome reg b */
- #define mem_besrsb 0x0c /* bus error syndrome reg set b */
- #define mem_bear 0x10 /* bus error address reg */
-#endif
- #define mem_mcopt1 0x20 /* memory controller options 1 */
- #define mem_status 0x24 /* memory status */
- #define mem_rtr 0x30 /* refresh timer reg */
- #define mem_pmit 0x34 /* power management idle timer */
- #define mem_mb0cf 0x40 /* memory bank 0 configuration */
- #define mem_mb1cf 0x44 /* memory bank 1 configuration */
-#ifndef CONFIG_405EP
- #define mem_mb2cf 0x48 /* memory bank 2 configuration */
- #define mem_mb3cf 0x4c /* memory bank 3 configuration */
-#endif
- #define mem_sdtr1 0x80 /* timing reg 1 */
-#ifndef CONFIG_405EP
- #define mem_ecccf 0x94 /* ECC configuration */
- #define mem_eccerr 0x98 /* ECC error status */
-#endif
-
#ifndef CONFIG_405EP
/******************************************************************************
* Decompression Controller
@@ -1281,393 +1254,6 @@
#if defined(CONFIG_405EX)
#define SDR0_SRST 0x0200
-#define SDRAM_BESR0 0x00
-#define SDRAM_BEARL 0x02
-#define SDRAM_BEARU 0x03
-#define SDRAM_WMIRQ 0x06 /**/
-#define SDRAM_PLBOPT 0x08 /**/
-#define SDRAM_PUABA 0x09 /**/
-#define SDRAM_MCSTAT 0x1F /* memory controller status */
-#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
-#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
-#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
-#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
-#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
-#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
-#define SDRAM_CODT 0x26 /* on die termination for controller */
-#define SDRAM_VVPR 0x27 /* variable VRef programmming */
-#define SDRAM_OPARS 0x28 /* on chip driver control setup */
-#define SDRAM_OPART 0x29 /* on chip driver control trigger */
-#define SDRAM_RTR 0x30 /* refresh timer */
-#define SDRAM_PMIT 0x34 /* power management idle timer */
-#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
-#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
-#define SDRAM_MB2CF 0x48 /* memory bank 2 configuration */
-#define SDRAM_MB3CF 0x4C /* memory bank 3 configuration */
-#define SDRAM_INITPLR0 0x50 /* manual initialization control */
-#define SDRAM_INITPLR1 0x51 /* manual initialization control */
-#define SDRAM_INITPLR2 0x52 /* manual initialization control */
-#define SDRAM_INITPLR3 0x53 /* manual initialization control */
-#define SDRAM_INITPLR4 0x54 /* manual initialization control */
-#define SDRAM_INITPLR5 0x55 /* manual initialization control */
-#define SDRAM_INITPLR6 0x56 /* manual initialization control */
-#define SDRAM_INITPLR7 0x57 /* manual initialization control */
-#define SDRAM_INITPLR8 0x58 /* manual initialization control */
-#define SDRAM_INITPLR9 0x59 /* manual initialization control */
-#define SDRAM_INITPLR10 0x5a /* manual initialization control */
-#define SDRAM_INITPLR11 0x5b /* manual initialization control */
-#define SDRAM_INITPLR12 0x5c /* manual initialization control */
-#define SDRAM_INITPLR13 0x5d /* manual initialization control */
-#define SDRAM_INITPLR14 0x5e /* manual initialization control */
-#define SDRAM_INITPLR15 0x5f /* manual initialization control */
-#define SDRAM_RQDC 0x70 /* read DQS delay control */
-#define SDRAM_RFDC 0x74 /* read feedback delay control */
-#define SDRAM_RDCC 0x78 /* read data capture control */
-#define SDRAM_DLCR 0x7A /* delay line calibration */
-#define SDRAM_CLKTR 0x80 /* DDR clock timing */
-#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
-#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
-#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
-#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
-#define SDRAM_MMODE 0x88 /* memory mode */
-#define SDRAM_MEMODE 0x89 /* memory extended mode */
-#define SDRAM_ECCCR 0x98 /* ECC error status */
-#define SDRAM_RID 0xF8 /* revision ID */
-
-/*-----------------------------------------------------------------------------+
-| Memory Bank 0-7 configuration
-+----------------------------------------------------------------------------*/
-#define SDRAM_RXBAS_SDSZ_MASK PPC_REG_VAL(19, 0xF)
-#define SDRAM_RXBAS_SDSZ_4MB PPC_REG_VAL(19, 0x0)
-#define SDRAM_RXBAS_SDSZ_8MB PPC_REG_VAL(19, 0x1)
-#define SDRAM_RXBAS_SDSZ_16MB PPC_REG_VAL(19, 0x2)
-#define SDRAM_RXBAS_SDSZ_32MB PPC_REG_VAL(19, 0x3)
-#define SDRAM_RXBAS_SDSZ_64MB PPC_REG_VAL(19, 0x4)
-#define SDRAM_RXBAS_SDSZ_128MB PPC_REG_VAL(19, 0x5)
-#define SDRAM_RXBAS_SDSZ_256MB PPC_REG_VAL(19, 0x6)
-#define SDRAM_RXBAS_SDSZ_512MB PPC_REG_VAL(19, 0x7)
-#define SDRAM_RXBAS_SDSZ_1024MB PPC_REG_VAL(19, 0x8)
-#define SDRAM_RXBAS_SDSZ_2048MB PPC_REG_VAL(19, 0x9)
-#define SDRAM_RXBAS_SDSZ_4096MB PPC_REG_VAL(19, 0xA)
-#define SDRAM_RXBAS_SDSZ_8192MB PPC_REG_VAL(19, 0xB)
-#define SDRAM_RXBAS_SDSZ_8 SDRAM_RXBAS_SDSZ_8MB
-#define SDRAM_RXBAS_SDSZ_16 SDRAM_RXBAS_SDSZ_16MB
-#define SDRAM_RXBAS_SDSZ_32 SDRAM_RXBAS_SDSZ_32MB
-#define SDRAM_RXBAS_SDSZ_64 SDRAM_RXBAS_SDSZ_64MB
-#define SDRAM_RXBAS_SDSZ_128 SDRAM_RXBAS_SDSZ_128MB
-#define SDRAM_RXBAS_SDSZ_256 SDRAM_RXBAS_SDSZ_256MB
-#define SDRAM_RXBAS_SDSZ_512 SDRAM_RXBAS_SDSZ_512MB
-#define SDRAM_RXBAS_SDSZ_1024 SDRAM_RXBAS_SDSZ_1024MB
-#define SDRAM_RXBAS_SDSZ_2048 SDRAM_RXBAS_SDSZ_2048MB
-#define SDRAM_RXBAS_SDSZ_4096 SDRAM_RXBAS_SDSZ_4096MB
-#define SDRAM_RXBAS_SDSZ_8192 SDRAM_RXBAS_SDSZ_8192MB
-#define SDRAM_RXBAS_SDAM_MODE0 PPC_REG_VAL(23, 0x0)
-#define SDRAM_RXBAS_SDAM_MODE1 PPC_REG_VAL(23, 0x1)
-#define SDRAM_RXBAS_SDAM_MODE2 PPC_REG_VAL(23, 0x2)
-#define SDRAM_RXBAS_SDAM_MODE3 PPC_REG_VAL(23, 0x3)
-#define SDRAM_RXBAS_SDAM_MODE4 PPC_REG_VAL(23, 0x4)
-#define SDRAM_RXBAS_SDAM_MODE5 PPC_REG_VAL(23, 0x5)
-#define SDRAM_RXBAS_SDAM_MODE6 PPC_REG_VAL(23, 0x6)
-#define SDRAM_RXBAS_SDAM_MODE7 PPC_REG_VAL(23, 0x7)
-#define SDRAM_RXBAS_SDAM_MODE8 PPC_REG_VAL(23, 0x8)
-#define SDRAM_RXBAS_SDAM_MODE9 PPC_REG_VAL(23, 0x9)
-#define SDRAM_RXBAS_SDBE_DISABLE PPC_REG_VAL(31, 0x0)
-#define SDRAM_RXBAS_SDBE_ENABLE PPC_REG_VAL(31, 0x1)
-
-/*-----------------------------------------------------------------------------+
-| Memory Controller Status
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
-#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
-#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
-#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */
-#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
-#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */
-
-/*-----------------------------------------------------------------------------+
-| Memory Controller Options 1
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask */
-#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
-#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
-#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */
-#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/
-#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3)
-#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
-#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
-#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
-#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
-#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
-#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
-#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
-#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
-#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
-#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
-#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
-#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
-#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
-#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */
-#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
-#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
-#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
-#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
-#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
-#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
-#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
-#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
-#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
-#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
-#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
-#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
-#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
-#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
-#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */
-
-/*-----------------------------------------------------------------------------+
-| Memory Controller Options 2
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
-#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
-#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
-#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
-#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
-#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
-#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
-#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
-#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */
-#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
-#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */
-#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */
-#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
-#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */
-#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */
-#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
-#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
-#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Refresh Timer Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RTR_RINT_MASK 0xFFF80000
-#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16)
-#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8)
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Read DQS Delay Control Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RQDC_RQDE_MASK 0x80000000
-#define SDRAM_RQDC_RQDE_DISABLE 0x00000000
-#define SDRAM_RQDC_RQDE_ENABLE 0x80000000
-#define SDRAM_RQDC_RQFD_MASK 0x000001FF
-#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
-
-#define SDRAM_RQDC_RQFD_MAX 0xFF
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Read Data Capture Control Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RDCC_RDSS_MASK 0xC0000000
-#define SDRAM_RDCC_RDSS_T1 0x00000000
-#define SDRAM_RDCC_RDSS_T2 0x40000000
-#define SDRAM_RDCC_RDSS_T3 0x80000000
-#define SDRAM_RDCC_RDSS_T4 0xC0000000
-#define SDRAM_RDCC_RSAE_MASK 0x00000001
-#define SDRAM_RDCC_RSAE_DISABLE 0x00000001
-#define SDRAM_RDCC_RSAE_ENABLE 0x00000000
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Read Feedback Delay Control Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RFDC_ARSE_MASK 0x80000000
-#define SDRAM_RFDC_ARSE_DISABLE 0x80000000
-#define SDRAM_RFDC_ARSE_ENABLE 0x00000000
-#define SDRAM_RFDC_RFOS_MASK 0x007F0000
-#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
-#define SDRAM_RFDC_RFFD_MASK 0x000003FF
-#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
-
-#define SDRAM_RFDC_RFFD_MAX 0x4FF
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Delay Line Calibration Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_DLCR_DCLM_MASK 0x80000000
-#define SDRAM_DLCR_DCLM_MANUEL 0x80000000
-#define SDRAM_DLCR_DCLM_AUTO 0x00000000
-#define SDRAM_DLCR_DLCR_MASK 0x08000000
-#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
-#define SDRAM_DLCR_DLCR_IDLE 0x00000000
-#define SDRAM_DLCR_DLCS_MASK 0x07000000
-#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
-#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
-#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
-#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
-#define SDRAM_DLCR_DLCS_ERROR 0x04000000
-#define SDRAM_DLCR_DLCV_MASK 0x000001FF
-#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
-#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF)
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Controller On Die Termination Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_CODT_ODT_ON 0x80000000
-#define SDRAM_CODT_ODT_OFF 0x00000000
-#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020
-#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000
-#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020
-#define SDRAM_CODT_DQS_MASK 0x00000010
-#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000
-#define SDRAM_CODT_DQS_SINGLE_END 0x00000010
-#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000
-#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
-#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
-#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
-#define SDRAM_CODT_IO_HIZ 0x00000000
-#define SDRAM_CODT_IO_NMODE 0x00000001
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Mode Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MMODE_WR_MASK 0x00000E00
-#define SDRAM_MMODE_WR_DDR1 0x00000000
-#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400
-#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600
-#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800
-#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00
-#define SDRAM_MMODE_DCL_MASK 0x00000070
-#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020
-#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060
-#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030
-#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020
-#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030
-#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040
-#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050
-#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060
-#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Extended Mode Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MEMODE_DIC_MASK 0x00000002
-#define SDRAM_MEMODE_DIC_NORMAL 0x00000000
-#define SDRAM_MEMODE_DIC_WEAK 0x00000002
-#define SDRAM_MEMODE_DLL_MASK 0x00000001
-#define SDRAM_MEMODE_DLL_DISABLE 0x00000001
-#define SDRAM_MEMODE_DLL_ENABLE 0x00000000
-#define SDRAM_MEMODE_RTT_MASK 0x00000044
-#define SDRAM_MEMODE_RTT_DISABLED 0x00000000
-#define SDRAM_MEMODE_RTT_75OHM 0x00000004
-#define SDRAM_MEMODE_RTT_150OHM 0x00000040
-#define SDRAM_MEMODE_DQS_MASK 0x00000400
-#define SDRAM_MEMODE_DQS_DISABLE 0x00000400
-#define SDRAM_MEMODE_DQS_ENABLE 0x00000000
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Clock Timing Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
-#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
-#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Write Timing Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_WRDTR_WDTP_1_CYC 0x80000000
-#define SDRAM_WRDTR_LLWP_MASK 0x10000000
-#define SDRAM_WRDTR_LLWP_DIS 0x10000000
-#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
-#define SDRAM_WRDTR_WTR_MASK 0x0E000000
-#define SDRAM_WRDTR_WTR_0_DEG 0x06000000
-#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
-#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
-
-/*-----------------------------------------------------------------------------+
-| SDRAM SDTR1 Options
-+-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR1_LDOF_MASK 0x80000000
-#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
-#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
-#define SDRAM_SDTR1_RTW_MASK 0x00F00000
-#define SDRAM_SDTR1_RTW_2_CLK 0x00200000
-#define SDRAM_SDTR1_RTW_3_CLK 0x00300000
-#define SDRAM_SDTR1_WTWO_MASK 0x000F0000
-#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
-#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
-#define SDRAM_SDTR1_RTRO_MASK 0x0000F000
-#define SDRAM_SDTR1_RTRO_1_CLK 0x00000000
-#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
-
-/*-----------------------------------------------------------------------------+
-| SDRAM SDTR2 Options
-+-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR2_RCD_MASK 0xF0000000
-#define SDRAM_SDTR2_RCD_1_CLK 0x10000000
-#define SDRAM_SDTR2_RCD_2_CLK 0x20000000
-#define SDRAM_SDTR2_RCD_3_CLK 0x30000000
-#define SDRAM_SDTR2_RCD_4_CLK 0x40000000
-#define SDRAM_SDTR2_RCD_5_CLK 0x50000000
-#define SDRAM_SDTR2_WTR_MASK 0x0F000000
-#define SDRAM_SDTR2_WTR_1_CLK 0x01000000
-#define SDRAM_SDTR2_WTR_2_CLK 0x02000000
-#define SDRAM_SDTR2_WTR_3_CLK 0x03000000
-#define SDRAM_SDTR2_WTR_4_CLK 0x04000000
-#define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
-#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
-#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000
-#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000
-#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000
-#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000
-#define SDRAM_SDTR2_WPC_MASK 0x0000F000
-#define SDRAM_SDTR2_WPC_2_CLK 0x00002000
-#define SDRAM_SDTR2_WPC_3_CLK 0x00003000
-#define SDRAM_SDTR2_WPC_4_CLK 0x00004000
-#define SDRAM_SDTR2_WPC_5_CLK 0x00005000
-#define SDRAM_SDTR2_WPC_6_CLK 0x00006000
-#define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12)
-#define SDRAM_SDTR2_RPC_MASK 0x00000F00
-#define SDRAM_SDTR2_RPC_2_CLK 0x00000200
-#define SDRAM_SDTR2_RPC_3_CLK 0x00000300
-#define SDRAM_SDTR2_RPC_4_CLK 0x00000400
-#define SDRAM_SDTR2_RP_MASK 0x000000F0
-#define SDRAM_SDTR2_RP_3_CLK 0x00000030
-#define SDRAM_SDTR2_RP_4_CLK 0x00000040
-#define SDRAM_SDTR2_RP_5_CLK 0x00000050
-#define SDRAM_SDTR2_RP_6_CLK 0x00000060
-#define SDRAM_SDTR2_RP_7_CLK 0x00000070
-#define SDRAM_SDTR2_RRD_MASK 0x0000000F
-#define SDRAM_SDTR2_RRD_2_CLK 0x00000002
-#define SDRAM_SDTR2_RRD_3_CLK 0x00000003
-
-/*-----------------------------------------------------------------------------+
-| SDRAM SDTR3 Options
-+-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR3_RAS_MASK 0x1F000000
-#define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
-#define SDRAM_SDTR3_RC_MASK 0x001F0000
-#define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
-#define SDRAM_SDTR3_XCS_MASK 0x00001F00
-#define SDRAM_SDTR3_XCS 0x00000D00
-#define SDRAM_SDTR3_RFC_MASK 0x0000003F
-#define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
-
-/*-----------------------------------------------------------------------------+
-| Memory Bank 0-1 configuration
-+-----------------------------------------------------------------------------*/
-#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
-#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
-#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
-#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
-#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
-#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
-#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
-#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
-#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
-#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
-#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
-#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
-#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
-#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
-
#define sdr_uart0 0x0120 /* UART0 Config */
#define sdr_uart1 0x0121 /* UART1 Config */
#define sdr_mfr 0x4300 /* SDR0_MFR reg */