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| author | Angelo Dureghello <sysamfw@gmail.com> | 2012-12-01 01:14:18 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2013-01-10 14:39:13 +0100 |
| commit | 07b2c5c0e5abb8b6b996068471024410a7ef4bd4 (patch) | |
| tree | 342e5c444db790da94d826f797cee723d9cfef21 /include/mpc5xx.h | |
| parent | 642ef40bdc95bef829ae3aadc217f829c4c298c4 (diff) | |
| download | u-boot-imx-07b2c5c0e5abb8b6b996068471024410a7ef4bd4.zip u-boot-imx-07b2c5c0e5abb8b6b996068471024410a7ef4bd4.tar.gz u-boot-imx-07b2c5c0e5abb8b6b996068471024410a7ef4bd4.tar.bz2 | |
mtd/cfi: add support for SST 4KB sector granularity
Add support for SST 4KB sector granularity.
Many recent SST flashes, i.e. SST39VF3201B and similar of this family
are declared CFI-conformant from SST. They support CFI query, but implement
2 different sector sizes in the same memory: a 64KB sector (they call it
"block", std AMD erase cmd=0x30), and a 4KB sector (they call it "sector",
erase cmd=0x50). Also, CFI query on these chips, reading from address 0x2dh
of cfi query struct, detects a number of secotrs for the 4KB granularity
(flinfo shows it).
For all other aspects, they are CFI compliant, so, as Linux do, i think
it's a good idea to handle these chips in the CFI driver, with a fixup
to allow 4KB granularity, as should be expected, instead of 64KB.
Signed-off-by: Angelo Dureghello <sysamfw@gmail.com>
Signed-off-by: Stefan Rose <sr@denx.de>
Diffstat (limited to 'include/mpc5xx.h')
0 files changed, 0 insertions, 0 deletions