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| author | ebony.zhu@freescale.com <ebony.zhu@freescale.com> | 2006-12-18 16:25:15 +0800 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2007-04-23 19:58:27 -0500 |
| commit | 39b18c4f3e0b6d0dc00f4e68bad2da3766c85f09 (patch) | |
| tree | df783cf7d54f509c2202875f506c937509822947 /include/lpd7a400_cpld.h | |
| parent | 41fb7e0f1ec9b91bdae2565bab5f2e3ee15039c7 (diff) | |
| download | u-boot-imx-39b18c4f3e0b6d0dc00f4e68bad2da3766c85f09.zip u-boot-imx-39b18c4f3e0b6d0dc00f4e68bad2da3766c85f09.tar.gz u-boot-imx-39b18c4f3e0b6d0dc00f4e68bad2da3766c85f09.tar.bz2 | |
u-boot: Disables MPC8548CDS 2T_TIMING for DDR by default
This patch disables MPC8548CDS 2T_TIMING for DDR by default.
Signed-off-by:Ebony Zhu <ebony.zhu@freescale.com>
Diffstat (limited to 'include/lpd7a400_cpld.h')
0 files changed, 0 insertions, 0 deletions