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| author | Shengzhou Liu <Shengzhou.Liu@nxp.com> | 2016-08-26 18:30:38 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-09-14 14:05:20 -0700 |
| commit | 1a87c24fe8f4c8afc735aa50b8fc9eaa2f230c0f (patch) | |
| tree | 3977d2c8cae7f96374254e30a4125409fcb256fd /include/fsl_immap.h | |
| parent | 77b571da3b2c2fd46d6a80e4e045f3aae392d979 (diff) | |
| download | u-boot-imx-1a87c24fe8f4c8afc735aa50b8fc9eaa2f230c0f.zip u-boot-imx-1a87c24fe8f4c8afc735aa50b8fc9eaa2f230c0f.tar.gz u-boot-imx-1a87c24fe8f4c8afc735aa50b8fc9eaa2f230c0f.tar.bz2 | |
armv8: fsl-layerscape: Update ddr erratum a008336
DDR erratum A008336 only applies to DDR controller v5.2.0.
DDR controller v5.2.1 already has default 0x43b30002 in
EDDRTQCR1 register for optimal performance.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'include/fsl_immap.h')
0 files changed, 0 insertions, 0 deletions