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authorMarek Vasut <marex@denx.de>2014-10-22 21:56:01 +0200
committerJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>2014-10-27 22:37:03 +0530
commit80d73338080c83e17fbf3f844052ec71d03ecd13 (patch)
tree636e9c4eefe012c66d1072e1fc80f82e4115a978 /include/fpga.h
parent37dcc130e0c804da6ad50bf273d0d737cfe9cf8f (diff)
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spi: altera: Zap endless loop
The driver contained an endless loop when waiting for TX completion, this is a bad idea since if the hardware fails, the loop might spin forever. Add timeout and handle it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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