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| author | Alban Bedel <alban.bedel@avionic-design.de> | 2013-11-20 17:42:46 +0100 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2013-12-18 10:19:49 -0700 |
| commit | 766afc3dff35f8f257deb0373735a328c8206880 (patch) | |
| tree | 2813b7f9f6934e88dcb4831f49474eafd0837842 /include/ec_commands.h | |
| parent | 8f38038193752d3719f39ccd562f7ffdf83989d5 (diff) | |
| download | u-boot-imx-766afc3dff35f8f257deb0373735a328c8206880.zip u-boot-imx-766afc3dff35f8f257deb0373735a328c8206880.tar.gz u-boot-imx-766afc3dff35f8f257deb0373735a328c8206880.tar.bz2 | |
arm: tegra: Fix the CPU complex reset masks
The CPU complex reset masks are not matching with the datasheet for
the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20
and T30 the register consist of groups of 4 bits, with one bit for
each CPU core. On T20 the 2 high bits of each group are always stubbed
as there is only 2 cores.
Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swrren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'include/ec_commands.h')
0 files changed, 0 insertions, 0 deletions