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| author | Tom Warren <twarren@nvidia.com> | 2015-06-25 09:50:44 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-08-05 15:22:51 -0700 |
| commit | 722e000ccd7226c5cd071590b5361620eb0b126c (patch) | |
| tree | 257ddcaf4039dd6722e743e8a1f4035c2f85387f /include/dt-bindings/reset/altr,rst-mgr.h | |
| parent | 3e8650c0f9cc7fb29bd75c11d0173768fcc80203 (diff) | |
| download | u-boot-imx-722e000ccd7226c5cd071590b5361620eb0b126c.zip u-boot-imx-722e000ccd7226c5cd071590b5361620eb0b126c.tar.gz u-boot-imx-722e000ccd7226c5cd071590b5361620eb0b126c.tar.bz2 | |
Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Added PLL variables (dividers mask/shift, lock enable/detect, etc.)
to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X.
Used pllinfo struct in all clock functions, validated on T210.
Should be equivalent to prior code on T124/114/30/20. Thanks
to Marcel Ziswiler for corrections to the T20/T30 values.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'include/dt-bindings/reset/altr,rst-mgr.h')
0 files changed, 0 insertions, 0 deletions