Merge branch 'u-boot/master' into 'u-boot-arm/master'

author: Albert ARIBAUD <albert.u.boot@aribaud.net> 2015-05-05 10:09:06 +0200
committer: Albert ARIBAUD <albert.u.boot@aribaud.net> 2015-05-05 10:09:06 +0200
commit: b939689c7b87773c44275a578ffc8674a867e39d (patch)
tree: 785d71eb0bbc707385e4456a14b21706223d99a3 /include/configs
parent: 97840b5d1fe0960134c3553a9d9d1c1cd1be784d (diff)
parent: ace97d26176a3ebc9ec07738450de93eea35975c (diff)
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86 files changed, 2373 insertions, 351 deletions
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index 9390464..7eac03b 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -180,6 +180,10 @@
 #define CONFIG_ENV_SECT_SIZE		0x2000
 #define CONFIG_ENV_IS_IN_FLASH		1
 
+#define LDS_BOARD_TEXT \
+        . = DEFINED(env_offset) ? env_offset : .; \
+        common/env_embedded.o (.text*);
+
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index e9424b4..ce33ba4 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -267,6 +267,10 @@
 #	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
 #endif
 
+#define LDS_BOARD_TEXT \
+        arch/m68k/cpu/mcf5227x/built-in.o   (.text*) \
+	arch/m68k/lib/built-in.o            (.text*)
+
 /*
  * This is setting for JFFS2 support in u-boot.
  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index 883347b..4bba815 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -199,6 +199,11 @@
  * Environment is embedded in u-boot in the second sector of the flash
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
+
+#define LDS_BOARD_TEXT \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	common/env_embedded.o (.text);
+
 #ifdef NORFLASH_PS32BIT
 #	define CONFIG_ENV_OFFSET		(0x8000)
 #	define CONFIG_ENV_SIZE		0x4000
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index 60e5b45..6167ea1 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -91,6 +91,11 @@
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_ENV_IS_IN_FLASH	1
+
+#define LDS_BOARD_TEXT \
+        . = DEFINED(env_offset) ? env_offset : .; \
+        common/env_embedded.o (.text);
+
 #define CONFIG_ENV_OFFSET		0x4000	/* Address of Environment Sector*/
 #define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 #define CONFIG_ENV_SECT_SIZE	0x2000 /* see README - env sector total size	*/
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index 7421b57..5d97874 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -32,6 +32,10 @@
 #	define CONFIG_ENV_IS_IN_FLASH	1
 #endif
 
+#define LDS_BOARD_TEXT \
+        . = DEFINED(env_offset) ? env_offset : .; \
+        common/env_embedded.o (.text*);
+
 /*
  * Command line configuration.
  */
diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
index 8fd3907..64dc64d 100644
--- a/include/configs/M5253EVBE.h
+++ b/include/configs/M5253EVBE.h
@@ -33,6 +33,11 @@
 #define CONFIG_ENV_IS_IN_FLASH	1
 #endif
 
+#define LDS_BOARD_TEXT \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	common/env_embedded.o      (.text)
+
+
 /*
  * BOOTP options
  */
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index 2c056b1..159d2f8 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -41,6 +41,10 @@
 #define CONFIG_ENV_IS_IN_FLASH	1
 #endif
 
+#define LDS_BOARD_TEXT \
+        . = DEFINED(env_offset) ? env_offset : .; \
+        common/env_embedded.o (.text);
+
 /*
  * BOOTP options
  */
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 7eb3172..14ccddb 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -42,6 +42,10 @@
 #define CONFIG_ENV_IS_IN_FLASH	1
 #endif
 
+#define LDS_BOARD_TEXT \
+        . = DEFINED(env_offset) ? env_offset : .; \
+        common/env_embedded.o (.text);
+
 /*
  * BOOTP options
  */
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index 569ad42..bc740ae 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -32,6 +32,10 @@
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_IS_IN_FLASH	1
 
+#define LDS_BOARD_TEXT \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	common/env_embedded.o (.text*);
+
 /*
  * BOOTP options
  */
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index e3fa856..0829708 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -205,6 +205,10 @@
 #define CONFIG_ENV_SECT_SIZE		0x8000
 #define CONFIG_ENV_IS_IN_FLASH		1
 
+#define LDS_BOARD_TEXT \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	common/env_embedded.o       (.text*)
+
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 795f359..a42b5f6 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -209,6 +209,10 @@
 #define CONFIG_ENV_SECT_SIZE	0x2000
 #define CONFIG_ENV_IS_IN_FLASH	1
 
+#define LDS_BOARD_TEXT \
+        . = DEFINED(env_offset) ? env_offset : .; \
+        common/env_embedded.o (.text*);
+
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index d75b43c..c142dfb 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -209,6 +209,10 @@
 #define CONFIG_ENV_SECT_SIZE	0x2000
 #define CONFIG_ENV_IS_IN_FLASH	1
 
+#define LDS_BOARD_TEXT \
+        . = DEFINED(env_offset) ? env_offset : .; \
+        common/env_embedded.o (.text*);
+
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index a0d7d52..9f755e5 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -255,7 +255,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	 /* Reserved for malloc */
 
 /* Serial Port */
@@ -602,7 +602,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  */
 #ifndef CONFIG_SYS_RAMBOOT
     #define CONFIG_ENV_IS_IN_FLASH	1
-    #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x60000)
+    #define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
     #define CONFIG_ENV_SECT_SIZE		0x10000	/* 64K(one sector) for env */
 #else
     #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index faaf22c..107efdc 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -140,6 +140,11 @@
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+
 #ifndef CONFIG_SYS_NO_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
@@ -448,6 +453,17 @@ unsigned long get_board_ddr_clk(void);
 #define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
 #define I2C_MUX_CH_DEFAULT	0x8
 
+#define I2C_MUX_CH_VOL_MONITOR	0xa
+
+#define CONFIG_VID_FLS_ENV		"t208xrdb_vdd_mv"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_VID
+#endif
+#define CONFIG_VOL_MONITOR_IR36021_SET
+#define CONFIG_VOL_MONITOR_IR36021_READ
+/* The lowest and highest voltage allowed for T208xRDB */
+#define VDD_MV_MIN			819
+#define VDD_MV_MAX			1212
 
 /*
  * RapidIO
@@ -646,8 +662,8 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_AQUANTIA
 #define CONFIG_PHY_CORTINA
-#define CONFIG_PHY_AQ1202
 #define CONFIG_PHY_REALTEK
 #define CONFIG_CORTINA_FW_LENGTH	0x40000
 #define RGMII_PHY1_ADDR		0x01  /* RealTek RTL8211E */
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index c1ad35a..957a436 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -638,6 +638,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_CORTINA
+#define CONFIG_SYS_CORTINA_FW_IN_NOR
 #define CONFIG_CORTINA_FW_ADDR		0xefe00000
 #define CONFIG_CORTINA_FW_LENGTH	0x40000
 #define CONFIG_PHY_TERANETICS
diff --git a/include/configs/amcore.h b/include/configs/amcore.h
index 229fa5a..5a06311 100644
--- a/include/configs/amcore.h
+++ b/include/configs/amcore.h
@@ -98,6 +98,10 @@
 #define CONFIG_ENV_SIZE			0x1000
 #define CONFIG_ENV_SECT_SIZE		0x1000
 
+#define LDS_BOARD_TEXT \
+        . = DEFINED(env_offset) ? env_offset : .; \
+        common/env_embedded.o (.text*);
+
 /* memory map space for linux boot data */
 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
 
diff --git a/include/configs/aristainetos.h b/include/configs/aristainetos.h
index 3066fd0..cc26790 100644
--- a/include/configs/aristainetos.h
+++ b/include/configs/aristainetos.h
@@ -262,6 +262,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_SYS_I2C_SLAVE		0x7f
 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x00} }
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index de837cf..7b9ff8f 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -343,6 +343,10 @@
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
 #define CONFIG_SYS_FLASH_CFI_NONBLOCK	1
 
+#define LDS_BOARD_TEXT \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	common/env_embedded.o       (.text*)
+
 #if ENABLE_JFFS
 /* JFFS Partition offset set */
 #define CONFIG_SYS_JFFS2_FIRST_BANK    0
diff --git a/include/configs/axs101.h b/include/configs/axs101.h
index 8a7095c..389f75b 100644
--- a/include/configs/axs101.h
+++ b/include/configs/axs101.h
@@ -116,7 +116,6 @@
 /*
  * Ethernet configuration
  */
-#define CONFIG_DESIGNWARE_ETH
 #define CONFIG_DW_AUTONEG
 #define CONFIG_NET_MULTI
 
diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h
index 878009f..7507d57 100644
--- a/include/configs/bf609-ezkit.h
+++ b/include/configs/bf609-ezkit.h
@@ -71,7 +71,6 @@
 #define CONFIG_NETCONSOLE
 #define CONFIG_NET_MULTI
 #define CONFIG_HOSTNAME		"bf609-ezkit"
-#define CONFIG_DESIGNWARE_ETH
 #define CONFIG_PHY_ADDR		1
 #define CONFIG_DW_PORTS		1
 #define CONFIG_DW_ALTDESCRIPTOR
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
index 7b460e8..5265787 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -14,65 +14,6 @@
 #define __CONFIG_H
 
 #include <configs/x86-common.h>
-
-
-#define CONFIG_SYS_MONITOR_LEN			(1 << 20)
-
-#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE		0x4000
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_NR_DRAM_BANKS			8
-#define CONFIG_X86_MRC_ADDR			0xfffa0000
-#define CONFIG_CACHE_MRC_SIZE_KB		512
-
-#define CONFIG_X86_SERIAL
-
-#define CONFIG_SCSI_DEV_LIST		{PCI_VENDOR_ID_INTEL, \
-			PCI_DEVICE_ID_INTEL_NM10_AHCI},	      \
-	{PCI_VENDOR_ID_INTEL,		\
-			PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
-	{PCI_VENDOR_ID_INTEL, \
-			PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
-	{PCI_VENDOR_ID_INTEL,		\
-			PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
-
-#define CONFIG_X86_OPTION_ROM_FILE		pci8086,0166.bin
-#define CONFIG_X86_OPTION_ROM_ADDR		0xfff90000
-
-#define CONFIG_PCI_MEM_BUS	0xe0000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_PREF_BUS	0xd0000000
-#define CONFIG_PCI_PREF_PHYS	CONFIG_PCI_PREF_BUS
-#define CONFIG_PCI_PREF_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x1000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0xefff
-
-#define CONFIG_SYS_EARLY_PCI_INIT
-#define CONFIG_PCI_PNP
-
-#define CONFIG_BIOSEMU
-#define VIDEO_IO_OFFSET				0
-#define CONFIG_X86EMU_RAW_IO
-
-#define CONFIG_CROS_EC
-#define CONFIG_CROS_EC_LPC
-#define CONFIG_CMD_CROS_EC
-#define CONFIG_ARCH_EARLY_INIT_R
-
-#undef CONFIG_ENV_IS_NOWHERE
-#undef CONFIG_ENV_SIZE
-#define CONFIG_ENV_SIZE			0x1000
-#define CONFIG_ENV_SECT_SIZE		0x1000
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET		0x003f8000
-
-#define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,serial\0" \
-					"stdout=vga,serial\0" \
-					"stderr=vga,serial\0"
+#include <configs/x86-chromebook.h>
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/chromebox_panther.h b/include/configs/chromebox_panther.h
new file mode 100644
index 0000000..00fe26d
--- /dev/null
+++ b/include/configs/chromebox_panther.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+#include <configs/x86-chromebook.h>
+
+#define CONFIG_RTL8169
+/* Avoid a warning in the Realtek Ethernet driver */
+#define CONFIG_SYS_CACHELINE_SIZE 16
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 4207504..d6e5a2b 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -245,6 +245,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_SYS_MXC_I2C3_SPEED	400000
 
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index b9f0b0b..38fcc40 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -104,6 +104,9 @@
 #define CONFIG_ENV_IS_IN_FLASH	1
 #endif
 
+#define LDS_BOARD_TEXT \
+        . = DEFINED(env_offset) ? env_offset : .; \
+        common/env_embedded.o (.text);
 
 /*
  * BOOTP options
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
new file mode 100644
index 0000000..414600a
--- /dev/null
+++ b/include/configs/colibri_vf.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright 2015 Toradex, Inc.
+ *
+ * Configuration settings for the Toradex VF50/VF61 module.
+ *
+ * Based on vf610twr.h:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_VF610
+#define CONFIG_SYS_THUMB_BUILD
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_USE_ARCH_MEMSET
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_FSL_LPUART
+#define LPUART_BASE			UART0_BASE
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_CMD_ASKENV
+
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_VF610_NFC
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR
+
+/* Dynamic MTD partition support */
+#define CONFIG_CMD_MTDPARTS	/* Enable 'mtdparts' command line support */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define MTDIDS_DEFAULT		"nand0=vf610_nfc"
+#define MTDPARTS_DEFAULT	"mtdparts=vf610_nfc:"		\
+				"128k(vf-bcb)ro,"		\
+				"1408k(u-boot)ro,"		\
+				"512k(u-boot-env),"		\
+				"-(ubi)"
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT3
+#define CONFIG_CMD_EXT4
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_UBI
+#define CONFIG_MTD_UBI_FASTMAP
+#define CONFIG_CMD_UBIFS	/* increases size by almost 60 KB */
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET1_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_FEC_MXC_PHYADDR          0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+
+#define CONFIG_IPADDR		192.168.10.2
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_SERVERIP		192.168.10.1
+
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_LOADADDR			0x80008000
+#define CONFIG_FDTADDR			0x84000000
+
+/* We boot from the gfxRAM area of the OCRAM. */
+#define CONFIG_SYS_TEXT_BASE		0x3f408000
+#define CONFIG_BOARD_SIZE_LIMIT		524288
+
+#define SD_BOOTCMD \
+	"sdargs=root=/dev/mmcblk0p2 rw rootwait\0"	\
+	"sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \
+	"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
+	"load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \
+	"load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
+	"bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#define NFS_BOOTCMD \
+	"nfsargs=ip=:::::eth0: root=/dev/nfs\0"	\
+	"nfsboot=run setup; " \
+	"setenv bootargs ${defargs} ${nfsargs} ${mtdparts} " \
+	"${setupargs} ${vidargs}; echo Booting from NFS...;" \
+	"dhcp ${kernel_addr_r} && "	\
+	"tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
+	"bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#define UBI_BOOTCMD	\
+	"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
+	"ubi.fm_autoconvert=1\0" \
+	"ubiboot=run setup; " \
+	"setenv bootargs ${defargs} ${ubiargs} ${mtdparts} "   \
+	"${setupargs} ${vidargs}; echo Booting from NAND...; " \
+	"ubi part ubi && ubifsmount ubi0:rootfs && " \
+	"ubifsload ${kernel_addr_r} /boot/${kernel_file} && " \
+	"ubifsload ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
+	"bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot"
+
+#define DFU_ALT_NAND_INFO "vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel_addr_r=0x82000000\0" \
+	"fdt_addr_r=0x84000000\0" \
+	"kernel_file=zImage\0" \
+	"fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \
+	"fdt_board=eval-v3\0" \
+	"defargs=\0" \
+	"console=ttyLP0\0" \
+	"setup=setenv setupargs " \
+	"console=tty1 console=${console}" \
+	",${baudrate}n8 ${memargs}\0" \
+	"setsdupdate=mmc rescan && set interface mmc && " \
+	"fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
+	"source ${loadaddr}\0" \
+	"setusbupdate=usb start && set interface usb && " \
+	"fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
+	"source ${loadaddr}\0" \
+	"setupdate=run setsdupdate || run setusbupdate\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
+	SD_BOOTCMD \
+	NFS_BOOTCMD \
+	UBI_BOOTCMD
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"Colibri VFxx # "
+#undef CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		\
+			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80010000
+#define CONFIG_SYS_MEMTEST_END		0x87C00000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE		(128 * 1024)	/* regular stack */
+
+/* Physical memory map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			(0x80000000)
+#define PHYS_SDRAM_SIZE			(256 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_OFFSET		(12 * 64 * 1024)
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			(64 * 2048)
+#define CONFIG_ENV_RANGE		(4 * 64 * 2048)
+#define CONFIG_ENV_OFFSET		(12 * 64 * 2048)
+#endif
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+/* USB Host Support */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_VF
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+/* USB Client Support */
+#define CONFIG_USB_GADGET
+#define CONFIG_CI_UDC
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW      2
+#define CONFIG_TRDX_VID                  0x1B67
+#define CONFIG_TRDX_PID_COLIBRI_VF50     0x0016
+#define CONFIG_TRDX_PID_COLIBRI_VF61     0x0017
+#define CONFIG_TRDX_PID_COLIBRI_VF61IT   0x0018
+#define CONFIG_TRDX_PID_COLIBRI_VF50IT   0x0019
+#define CONFIG_G_DNL_MANUFACTURER        "Toradex"
+#define CONFIG_G_DNL_VENDOR_NUM          CONFIG_TRDX_VID
+#define CONFIG_G_DNL_PRODUCT_NUM         CONFIG_TRDX_PID_COLIBRI_VF50
+
+/* USB DFU */
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_CMD_DFU
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_NAND
+#define CONFIG_DFU_MMC
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024 * 1024)
+
+/* USB Storage */
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_CMD_USB_MASS_STORAGE
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index 1683a15..4dd7b11 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -37,7 +37,7 @@
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MVTWSI
-#define CONFIG_I2C_MVTWSI_BASE		MVEBU_TWSI_BASE
+#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
 #define CONFIG_SYS_I2C_SLAVE		0x0
 #define CONFIG_SYS_I2C_SPEED		100000
 
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index e78cc69..d79612b 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -84,6 +84,14 @@
 	DFU_ALT_INFO_EMMC \
 	DFU_ALT_INFO_RAM
 
+/* Fastboot */
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_USB_FASTBOOT_BUF_ADDR    CONFIG_SYS_LOAD_ADDR
+#define CONFIG_USB_FASTBOOT_BUF_SIZE    0x2F000000
+#define CONFIG_FASTBOOT_FLASH
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV   1
+
 #include <configs/ti_omap5_common.h>
 
 /* Enhance our eMMC support / experience. */
@@ -182,8 +190,8 @@
 #define CONFIG_USBDOWNLOAD_GADGET
 #define CONFIG_USB_GADGET_VBUS_DRAW 2
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
-#define CONFIG_G_DNL_VENDOR_NUM 0x0403
-#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
+#define CONFIG_G_DNL_VENDOR_NUM 0x0451
+#define CONFIG_G_DNL_PRODUCT_NUM 0xd022
 #define CONFIG_USB_GADGET_DUALSPEED
 
 /* USB Device Firmware Update support */
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index 5ce01fb..bd08740 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -208,7 +208,7 @@
 #ifdef CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MVTWSI
-#define CONFIG_I2C_MVTWSI_BASE		ORION5X_TWSI_BASE
+#define CONFIG_I2C_MVTWSI_BASE0		ORION5X_TWSI_BASE
 #define CONFIG_SYS_I2C_SLAVE		0x0
 #define CONFIG_SYS_I2C_SPEED		100000
 #endif
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index b4b3ae8..e9f5bed 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -55,6 +55,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
 
 /* USB Configs */
diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h
index ae0e5ff..95e96ec 100644
--- a/include/configs/exynos5250-common.h
+++ b/include/configs/exynos5250-common.h
@@ -28,16 +28,6 @@
 
 #define CONFIG_SYS_INIT_SP_ADDR	CONFIG_IRAM_STACK
 
-/* Sound */
-#define CONFIG_CMD_SOUND
-#ifdef CONFIG_CMD_SOUND
-#define CONFIG_SOUND
-#define CONFIG_I2S_SAMSUNG
-#define CONFIG_I2S
-#define CONFIG_SOUND_MAX98095
-#define CONFIG_SOUND_WM8994
-#endif
-
 /* I2C */
 #define CONFIG_MAX_I2C_NUM	8
 
diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h
index b42dab7..3b1ac2c 100644
--- a/include/configs/exynos5420-common.h
+++ b/include/configs/exynos5420-common.h
@@ -15,8 +15,6 @@
 
 #include <configs/exynos5-common.h>
 
-#define CONFIG_ARCH_EARLY_INIT_R
-
 #define MACH_TYPE_SMDK5420	8002
 #define CONFIG_MACH_TYPE	MACH_TYPE_SMDK5420
 
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 854ae90..5f7cad8 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -52,6 +52,7 @@
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_SPD_BUS_NUM		2 /* I2C3 */
 #define CONFIG_SYS_MXC_I2C3_SLAVE	0xfe
 #define CONFIG_MXC_SPI
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 620f950..fcfc1b3 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -95,9 +95,11 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_I2C_GSC			0
 #define CONFIG_I2C_PMIC			1
+#define CONFIG_I2C_EDID
 
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
@@ -111,15 +113,12 @@
 
 /* Filesystem support */
 #define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_UBIFS
 #define CONFIG_DOS_PARTITION
 
-/* Network config - Allow larger/faster download for TFTP/NFS */
-#define CONFIG_IP_DEFRAG
-#define CONFIG_TFTP_BLOCKSIZE 4096
-#define CONFIG_NFS_READ_SIZE  4096
-
 /*
  * SATA Configs
  */
@@ -179,10 +178,10 @@
 
 /* Ethernet support */
 #define CONFIG_FEC_MXC
+#define CONFIG_E1000
 #define CONFIG_MII
 #define IMX_FEC_BASE             ENET_BASE_ADDR
 #define CONFIG_FEC_XCV_TYPE      RGMII
-#define CONFIG_ETHPRIME          "FEC"
 #define CONFIG_FEC_MXC_PHYADDR   0
 #define CONFIG_PHYLIB
 #define CONFIG_ARP_TIMEOUT       200UL
@@ -208,6 +207,18 @@
 #define CONFIG_NETCONSOLE
 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
 
+/* USB Mass Storage Gadget */
+#define CONFIG_USB_GADGET
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_USB_GADGET_VBUS_DRAW    2
+
+/* Netchip IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
+#define CONFIG_G_DNL_MANUFACTURER "Gateworks"
+
 /* Framebuffer and LCD */
 #define CONFIG_VIDEO
 #define CONFIG_VIDEO_IPUV3
@@ -316,6 +327,7 @@
 	"dio0:mode=gpio;dio1:mode=gpio;dio2:mode=gpio;dio3:mode=gpio\0" \
 
 #define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
+	"usb_pgood_delay=2000\0" \
 	"console=ttymxc1\0" \
 	"bootdevs=usb mmc sata flash\0" \
 	HWCONFIG_DEFAULT \
@@ -326,28 +338,30 @@
 	\
 	"fdt_high=0xffffffff\0" \
 	"fdt_addr=0x18000000\0" \
+	"initrd_high=0xffffffff\0" \
+	"bootdir=boot\0" \
 	"loadfdt=" \
-		"if ${fsload} ${fdt_addr} boot/${fdt_file}; then " \
-			"echo Loaded DTB from boot/${fdt_file}; " \
-		"elif ${fsload} ${fdt_addr} boot/${fdt_file1}; then " \
-			"echo Loaded DTB from boot/${fdt_file1}; " \
-		"elif ${fsload} ${fdt_addr} boot/${fdt_file2}; then " \
-				"echo Loaded DTB from boot/${fdt_file2}; " \
+		"if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then " \
+			"echo Loaded DTB from ${bootdir}/${fdt_file}; " \
+		"elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then " \
+			"echo Loaded DTB from ${bootdir}/${fdt_file1}; " \
+		"elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then " \
+			"echo Loaded DTB from ${bootdir}/${fdt_file2}; " \
 		"fi\0" \
 	\
-	"script=boot/6x_bootscript-ventana\0" \
+	"script=6x_bootscript-ventana\0" \
 	"loadscript=" \
-		"if ${fsload} ${loadaddr} ${script}; then " \
+		"if ${fsload} ${loadaddr} ${bootdir}/${script}; then " \
 			"source; " \
 		"fi\0" \
 	\
-	"uimage=boot/uImage\0" \
+	"uimage=uImage\0" \
 	"mmc_root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw\0" \
 	"mmc_boot=" \
 		"setenv fsload 'ext2load mmc 0:1'; " \
 		"mmc dev 0 && mmc rescan && " \
 		"run loadscript; " \
-		"if ${fsload} ${loadaddr} ${uimage}; then " \
+		"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
 			"setenv bootargs console=${console},${baudrate} " \
 				"root=/dev/mmcblk0p1 rootfstype=ext4 " \
 				"rootwait rw ${video} ${extra}; " \
@@ -361,7 +375,7 @@
 	"sata_boot=" \
 		"setenv fsload 'ext2load sata 0:1'; sata init && " \
 		"run loadscript; " \
-		"if ${fsload} ${loadaddr} ${uimage}; then " \
+		"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
 			"setenv bootargs console=${console},${baudrate} " \
 				"root=/dev/sda1 rootfstype=ext4 " \
 				"rootwait rw ${video} ${extra}; " \
@@ -374,7 +388,7 @@
 	"usb_boot=" \
 		"setenv fsload 'ext2load usb 0:1'; usb start && usb dev 0 && " \
 		"run loadscript; " \
-		"if ${fsload} ${loadaddr} ${uimage}; then " \
+		"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
 			"setenv bootargs console=${console},${baudrate} " \
 				"root=/dev/sda1 rootfstype=ext4 " \
 				"rootwait rw ${video} ${extra}; " \
@@ -417,8 +431,8 @@
 #else
 	#define CONFIG_EXTRA_ENV_SETTINGS \
 	CONFIG_EXTRA_ENV_SETTINGS_COMMON \
-	"image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \
 	\
+	"image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \
 	"nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \
 		"tftp ${loadaddr} ${image_rootfs} && " \
 		"nand erase.part rootfs && " \
@@ -426,12 +440,21 @@
 	\
 	"flash_boot=" \
 		"setenv fsload 'ubifsload'; " \
-		"ubi part rootfs && ubifsmount ubi0:rootfs; " \
+		"ubi part rootfs; " \
+		"if ubi check boot; then " \
+			"ubifsmount ubi0:boot; " \
+			"setenv root ubi0:rootfs ubi.mtd=2 " \
+				"rootfstype=squashfs,ubifs; " \
+			"setenv bootdir; " \
+		"elif ubi check rootfs; then " \
+			"ubifsmount ubi0:rootfs; " \
+			"setenv root ubi0:rootfs ubi.mtd=2 " \
+				"rootfstype=ubifs; " \
+		"fi; " \
 		"run loadscript; " \
-		"if ${fsload} ${loadaddr} ${uimage}; then " \
+		"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
 			"setenv bootargs console=${console},${baudrate} " \
-				"root=ubi0:rootfs ubi.mtd=2 " \
-				"rootfstype=ubifs ${video} ${extra}; " \
+				"root=${root} ${video} ${extra}; " \
 			"if run loadfdt && fdt addr ${fdt_addr}; then " \
 				"ubifsumount; " \
 				"bootm ${loadaddr} - ${fdt_addr}; " \
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index 49039d6..db197f3 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -38,6 +38,7 @@
 
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_CLK_OFFSET	I2C2_CLK_OFFSET
 
 #define CONFIG_MXC_UART
diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h
index 4362925..12c7382 100644
--- a/include/configs/integrator-common.h
+++ b/include/configs/integrator-common.h
@@ -7,8 +7,6 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#define CONFIG_INTEGRATOR
-
 #define CONFIG_SYS_TEXT_BASE		0x01000000
 #define CONFIG_SYS_MEMTEST_START	0x100000
 #define CONFIG_SYS_MEMTEST_END		0x10000000
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
index e168c8c..8439db7 100644
--- a/include/configs/integratorap.h
+++ b/include/configs/integratorap.h
@@ -18,7 +18,6 @@
 #include "integrator-common.h"
 
 /* Integrator/AP-specific configuration */
-#define CONFIG_ARCH_INTEGRATOR
 #define CONFIG_SYS_HZ_CLOCK		24000000	/* Timer 1 is clocked at 24Mhz */
 
 /*
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
index 7c1ef24..7518b60 100644
--- a/include/configs/integratorcp.h
+++ b/include/configs/integratorcp.h
@@ -18,7 +18,6 @@
 #include "integrator-common.h"
 
 /* Integrator CP-specific configuration */
-#define CONFIG_ARCH_CINTEGRATOR
 #define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer 1 is clocked at 1Mhz */
 
 /*
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 5de416d..9a8fd50 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -389,6 +389,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 
 /*
  * I2C bus multiplexer
@@ -655,6 +656,7 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_SECURE_BOOT
 #define CONFIG_CMD_BLOB
+#include <asm/fsl_secure_boot.h>
 #endif
 
 #endif
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index a13876b..729205f 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -205,6 +205,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 
 /* EEPROM */
 #ifndef CONFIG_SD_BOOT
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index e0435cc..e270fc8 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -19,8 +19,20 @@
 #define CONFIG_ARM_ERRATA_828024
 #define CONFIG_ARM_ERRATA_826974
 
+#include <asm/arch-fsl-lsch3/config.h>
+#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
+#define	CONFIG_SYS_HAS_SERDES
+#endif
+
+/* We need architecture specific misc initializations */
+#define CONFIG_ARCH_MISC_INIT
+
 /* Link Definitions */
-#define CONFIG_SYS_TEXT_BASE		0x30001000
+#ifdef CONFIG_SPL
+#define CONFIG_SYS_TEXT_BASE		0x80400000
+#else
+#define CONFIG_SYS_TEXT_BASE		0x30100000
+#endif
 
 #ifdef CONFIG_EMU
 #define CONFIG_SYS_NO_FLASH
@@ -39,13 +51,13 @@
 #define CONFIG_FIT
 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
 
+#ifndef CONFIG_SPL
 #define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
+#endif
 #ifndef CONFIG_SYS_FSL_DDR4
 #define CONFIG_SYS_FSL_DDR3		/* Use DDR3 memory */
 #define CONFIG_SYS_DDR_RAW_TIMING
 #endif
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	4
 
 #define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */
 
@@ -69,23 +81,26 @@
 #define CONFIG_SYS_DP_DDR_BASE_PHY	0
 #define CONFIG_DP_DDR_CTRL		2
 #define CONFIG_DP_DDR_NUM_CTRLS		1
-#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
 
 /* Generic Timer Definitions */
-#define COUNTER_FREQUENCY		12000000	/* 12MHz */
+/*
+ * This is not an accurate number. It is used in start.S. The frequency
+ * will be udpated later when get_bus_freq(0) is available.
+ */
+#define COUNTER_FREQUENCY		25000000	/* 25MHz */
 
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)
 
 /* I2C */
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_MXC_I2C1_SPEED	40000000
-#define CONFIG_SYS_MXC_I2C2_SPEED	40000000
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_MXC_I2C4		/* enable I2C bus 4 */
 
 /* Serial Port */
-#define CONFIG_CONS_INDEX       2
+#define CONFIG_CONS_INDEX       1
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE     1
@@ -96,131 +111,98 @@
 
 /* IFC */
 #define CONFIG_FSL_IFC
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+
 /*
- * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC
- * address 0. But this region is limited to 256MB. To accommodate bigger NOR
- * flash and other devices, we will map CS0 to 0x580000000 after relocation.
+ * During booting, IFC is mapped at the region of 0x30000000.
+ * But this region is limited to 256MB. To accommodate NOR, promjet
+ * and FPGA. This region is divided as below:
+ * 0x30000000 - 0x37ffffff : 128MB : NOR flash
+ * 0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
+ * 0x3C000000 - 0x40000000 : 64MB  : FPGA etc
+ *
+ * To accommodate bigger NOR flash and other devices, we will map IFC
+ * chip selects to as below:
+ * 0x5_1000_0000..0x5_1fff_ffff	Memory Hole
+ * 0x5_2000_0000..0x5_3fff_ffff	IFC CSx (FPGA, NAND and others 512MB)
+ * 0x5_4000_0000..0x5_7fff_ffff	ASIC or others 1GB
+ * 0x5_8000_0000..0x5_bfff_ffff	IFC CS0 1GB (NOR/Promjet)
+ * 0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
+ *
+ * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
  * CONFIG_SYS_FLASH_BASE has the final address (core view)
  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
  */
+
 #define CONFIG_SYS_FLASH_BASE			0x580000000ULL
 #define CONFIG_SYS_FLASH_BASE_PHYS		0x80000000
 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
 
-/*
- * NOR Flash Timing Params
- */
-#define CONFIG_SYS_NOR0_CSPR					\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
-	CSPR_PORT_SIZE_16					| \
-	CSPR_MSEL_NOR						| \
-	CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY				\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
-	CSPR_PORT_SIZE_16					| \
-	CSPR_MSEL_NOR						| \
-	CSPR_V)
-#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
-				FTIM0_NOR_TEADC(0x1) | \
-				FTIM0_NOR_TEAHC(0x1))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
-				FTIM1_NOR_TRAD_NOR(0x1))
-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x0) | \
-				FTIM2_NOR_TCH(0x0) | \
-				FTIM2_NOR_TWP(0x1))
-#define CONFIG_SYS_NOR_FTIM3	0x04000000
-#define CONFIG_SYS_IFC_CCR	0x01000000
+#define CONFIG_SYS_FLASH1_BASE_PHYS		0xC0000000
+#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY	0x8000000
 
 #ifndef CONFIG_SYS_NO_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#endif
 
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#ifndef __ASSEMBLY__
+unsigned long long get_qixis_addr(void);
 #endif
+#define QIXIS_BASE				get_qixis_addr()
+#define QIXIS_BASE_PHYS				0x20000000
+#define QIXIS_BASE_PHYS_EARLY			0xC000000
+#define QIXIS_STAT_PRES1			0xb
+#define QIXIS_SDID_MASK				0x07
+#define QIXIS_ESDHC_NO_ADAPTER			0x7
+
+#define CONFIG_SYS_NAND_BASE			0x530000000ULL
+#define CONFIG_SYS_NAND_BASE_PHYS		0x30000000
 
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_MAX_ECCPOS	256
-#define CONFIG_SYS_NAND_MAX_OOBFREE	2
-#define CONFIG_SYS_NAND_BASE		0x520000000
-#define CONFIG_SYS_NAND_BASE_PHYS	0x20000000
-
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
-				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
-				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
-				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
-
-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
-				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
-				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
-				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
-				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
-				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
-				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
-					FTIM0_NAND_TWP(0x18)   | \
-					FTIM0_NAND_TWCHT(0x07) | \
-					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
-					FTIM1_NAND_TWBE(0x39)  | \
-					FTIM1_NAND_TRR(0x0e)   | \
-					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
-					FTIM2_NAND_TREH(0x0a) | \
-					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
-
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_CMD_NAND
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
-
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+/* Debug Server firmware */
+#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE	(512UL * 1024 * 1024)
+/* 2 sec timeout */
+#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT			(2 * 1000 * 1000)
 
 /* MC firmware */
 #define CONFIG_FSL_MC_ENET
 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE	(512UL * 1024 * 1024)
-#define CONFIG_SYS_LS_MC_FW_IN_NOR
-#define CONFIG_SYS_LS_MC_FW_ADDR	0x580200000ULL
-#define CONFIG_SYS_LS_MC_DPL_IN_NOR
-#define CONFIG_SYS_LS_MC_DPL_ADDR	0x5806C0000ULL
 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
-#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	(256 * 1024)
-#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0xe00000
-
-/* Carve the MC private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_SYS_MEM_TOP_HIDE		mc_get_dram_block_size()
+#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
+#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
+
+/* Carve out a DDR region which will not be used by u-boot/Linux */
+#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
+#define CONFIG_SYS_MEM_TOP_HIDE		get_dram_size_to_hide()
 #endif
 
+/* PCIe */
+#define CONFIG_PCIE1		/* PCIE controler 1 */
+#define CONFIG_PCIE2		/* PCIE controler 2 */
+#define CONFIG_PCIE3		/* PCIE controler 3 */
+#define CONFIG_PCIE4		/* PCIE controler 4 */
+#define FSL_PCIE_COMPAT "fsl,20851a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS		0x40000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF	0x40000000
+#define CONFIG_SYS_PCIE_MEM_SIZE	0x40000000	/* 1G */
+
 /* Command line configuration */
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_BDI
@@ -228,6 +210,7 @@
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_IMI
+#define CONFIG_CMD_LOADB
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
@@ -237,8 +220,6 @@
 #define CONFIG_CMD_BOOTD
 #define CONFIG_CMD_ECHO
 #define CONFIG_CMD_SOURCE
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
@@ -247,9 +228,6 @@
 /* Physical Memory Map */
 /* fixme: these need to be checked against the board */
 #define CONFIG_CHIP_SELECTS_PER_CTRL	4
-#define CONFIG_SYS_CLK_FREQ	100000000
-#define CONFIG_DDR_CLK_FREQ	133333333
-
 
 #define CONFIG_NR_DRAM_BANKS		3
 
@@ -265,7 +243,7 @@
 	"kernel_addr=0x100000\0"		\
 	"ramdisk_addr=0x800000\0"		\
 	"ramdisk_size=0x2000000\0"		\
-	"fdt_high=0xffffffffffffffff\0"		\
+	"fdt_high=0xa0000000\0"			\
 	"initrd_high=0xffffffffffffffff\0"	\
 	"kernel_start=0x581200000\0"		\
 	"kernel_load=0xa0000000\0"		\
@@ -278,15 +256,11 @@
 				"hugepages=16"
 #define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
 					"$kernel_size && bootm $kernel_load"
-#define CONFIG_BOOTDELAY		1
-
-/* Store environment at top of flash */
-#define CONFIG_ENV_IS_NOWHERE		1
-#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_BOOTDELAY		10
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
-#define CONFIG_SYS_PROMPT		"> "
+#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_HUSH_PARSER
@@ -294,10 +268,36 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING		1
+#define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_MAXARGS		64	/* max command args */
 
 #ifndef __ASSEMBLY__
-unsigned long mc_get_dram_block_size(void);
+unsigned long get_dram_size_to_hide(void);
 #endif
 
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00100000
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_MAX_SIZE		0x16000
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_STACK		(CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_TEXT_BASE		0x1800a000
+
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x80400000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+
 #endif /* __LS2_COMMON_H */
diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2085a_emu.h
index a02d694..2d68e1b 100644
--- a/include/configs/ls2085a_emu.h
+++ b/include/configs/ls2085a_emu.h
@@ -12,6 +12,12 @@
 #define CONFIG_IDENT_STRING		" LS2085A-EMU"
 #define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2085A-EMU"
 
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	133333333
+
+#define CONFIG_SYS_MXC_I2C1_SPEED	40000000
+#define CONFIG_SYS_MXC_I2C2_SPEED	40000000
+
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_FSL_DDR_EMU		/* Support emulator */
 #define SPD_EEPROM_ADDRESS1	0x51
@@ -19,6 +25,65 @@
 #define SPD_EEPROM_ADDRESS3	0x53
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
 #define CONFIG_SYS_SPD_BUS_NUM	1	/* SPD on I2C bus 1 */
+#define CONFIG_DIMM_SLOTS_PER_CTLR		1
+#define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
 
 #define CONFIG_FSL_DDR_SYNC_REFRESH
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/*
+ * NOR Flash Timing Params
+ */
+#define CONFIG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
+				FTIM0_NOR_TEADC(0x1) | \
+				FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
+				FTIM1_NOR_TRAD_NOR(0x1))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x0) | \
+				FTIM2_NOR_TCH(0x0) | \
+				FTIM2_NOR_TWP(0x1))
+#define CONFIG_SYS_NOR_FTIM3	0x04000000
+#define CONFIG_SYS_IFC_CCR	0x01000000
+
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+
+/* Debug Server firmware */
+#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
+#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580C00000ULL
+
+/*
+ * This trick allows users to load MC images into DDR directly without
+ * copying from NOR flash. It dramatically improves speed.
+ */
+#define CONFIG_SYS_LS_MC_FW_IN_DDR
+#define CONFIG_SYS_LS_MC_DPL_IN_DDR
+#define CONFIG_SYS_LS_MC_DPC_IN_DDR
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_IS_NOWHERE		1
+#define CONFIG_ENV_SIZE			0x1000
+
 #endif /* __LS2_EMU_H */
diff --git a/include/configs/ls2085a_simu.h b/include/configs/ls2085a_simu.h
index af34f3f..d0d2eed 100644
--- a/include/configs/ls2085a_simu.h
+++ b/include/configs/ls2085a_simu.h
@@ -12,10 +12,112 @@
 #define CONFIG_IDENT_STRING		" LS2085A-SIMU"
 #define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2085A-SIMU"
 
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	133333333
+
+#define CONFIG_SYS_MXC_I2C1_SPEED	40000000
+#define CONFIG_SYS_MXC_I2C2_SPEED	40000000
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR		1
+#define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
+
 /* SMSC 91C111 ethernet configuration */
 #define CONFIG_SMC91111
 #define CONFIG_SMC91111_BASE	(0x2210000)
 
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+
+/*
+ * NOR Flash Timing Params
+ */
+#define CONFIG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
+				FTIM0_NOR_TEADC(0x1) | \
+				FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
+				FTIM1_NOR_TRAD_NOR(0x1))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x0) | \
+				FTIM2_NOR_TCH(0x0) | \
+				FTIM2_NOR_TWP(0x1))
+#define CONFIG_SYS_NOR_FTIM3	0x04000000
+#define CONFIG_SYS_IFC_CCR	0x01000000
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#endif
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
@@ -25,4 +127,24 @@
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
 
+/* Debug Server firmware */
+#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
+#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580C00000ULL
+
+/* MC firmware */
+#define CONFIG_SYS_LS_MC_FW_IN_NOR
+#define CONFIG_SYS_LS_MC_FW_ADDR	0x580200000ULL
+
+#define CONFIG_SYS_LS_MC_DPL_IN_NOR
+#define CONFIG_SYS_LS_MC_DPL_ADDR	0x5806C0000ULL
+
+#define CONFIG_SYS_LS_MC_DPC_IN_NOR
+#define CONFIG_SYS_LS_MC_DPC_ADDR	0x5806F8000ULL
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_IS_NOWHERE		1
+#define CONFIG_ENV_SIZE			0x1000
+
 #endif /* __LS2_SIMU_H */
diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
new file mode 100644
index 0000000..711d529
--- /dev/null
+++ b/include/configs/ls2085aqds.h
@@ -0,0 +1,359 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS2_QDS_H
+#define __LS2_QDS_H
+
+#include "ls2085a_common.h"
+#include <config_cmd_default.h>
+
+#define CONFIG_IDENT_STRING		" LS2085A-QDS"
+#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2085A-QDS"
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()
+#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ/4)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS3	0x53
+#define SPD_EEPROM_ADDRESS4	0x54
+#define SPD_EEPROM_ADDRESS5	0x55
+#define SPD_EEPROM_ADDRESS6	0x56	/* dummy address */
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
+#define CONFIG_DIMM_SLOTS_PER_CTLR		2
+#define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */
+
+/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
+#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)
+
+#define CONFIG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)	| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1a) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x04000000
+#define CONFIG_SYS_IFC_CCR	0x01000000
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
+					 CONFIG_SYS_FLASH_BASE + 0x40000000}
+#endif
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_LBMAP_SWITCH		0x06
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_LBMAP_NAND		0x09
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_RCW_SRC_NAND		0x107
+#define	QIXIS_RST_FORCE_MEM		0x01
+
+#define CONFIG_SYS_CSPR3_EXT	(0x0)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+
+#define CONFIG_SYS_AMASK3	IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
+					FTIM2_GPCM_TCH(0xf) | \
+					FTIM2_GPCM_TWP(0x3E))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR_EARLY
+#define CONFIG_SYS_CSPR2_FINAL		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK_EARLY
+#define CONFIG_SYS_AMASK2_FINAL		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		(896 * 1024)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR_EARLY
+#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK_EARLY
+#define CONFIG_SYS_AMASK1_FINAL		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x2000
+#endif
+
+/* Debug Server firmware */
+#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
+#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580D00000ULL
+
+/* MC firmware */
+#define CONFIG_SYS_LS_MC_FW_IN_NOR
+#define CONFIG_SYS_LS_MC_FW_ADDR	0x580300000ULL
+
+#define CONFIG_SYS_LS_MC_DPL_IN_NOR
+#define CONFIG_SYS_LS_MC_DPL_ADDR	0x580700000ULL
+
+#define CONFIG_SYS_LS_MC_DPC_IN_NOR
+#define CONFIG_SYS_LS_MC_DPC_ADDR	0x580800000ULL
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+
+/*
+ * I2C
+ */
+#define I2C_MUX_PCA_ADDR		0x77
+#define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
+
+/* I2C bus multiplexer */
+#define I2C_MUX_CH_DEFAULT      0x8
+
+/*
+ * MMC
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
+	QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
+#endif
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231               1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+#define CONFIG_FSL_MEMAC
+#define CONFIG_PCI		/* Enable PCIE */
+#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
+
+#ifdef CONFIG_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_E1000
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*  MMC  */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Initial environment variables */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x80100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0x581100000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x1000000\0"
+
+#ifdef CONFIG_FSL_MC_ENET
+#define CONFIG_FSL_MEMAC
+#define	CONFIG_PHYLIB
+#define CONFIG_PHYLIB_10G
+#define	CONFIG_CMD_MII
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"DPNI1"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+
+#endif
+
+#endif /* __LS2_QDS_H */
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
new file mode 100644
index 0000000..d1c2548
--- /dev/null
+++ b/include/configs/ls2085ardb.h
@@ -0,0 +1,305 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS2_RDB_H
+#define __LS2_RDB_H
+
+#include "ls2085a_common.h"
+#include <config_cmd_default.h>
+
+#define CONFIG_IDENT_STRING		" LS2085A-RDB"
+#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2085A-RDB"
+
+#undef CONFIG_CONS_INDEX
+#define CONFIG_CONS_INDEX       2
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ		133333333
+#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ/4)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS3	0x54
+#define SPD_EEPROM_ADDRESS4	0x53	/* Board error */
+#define SPD_EEPROM_ADDRESS5	0x55
+#define SPD_EEPROM_ADDRESS6	0x56	/* dummy address */
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
+#define CONFIG_DIMM_SLOTS_PER_CTLR		2
+#define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */
+
+/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
+#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)
+
+#define CONFIG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1a) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x04000000
+#define CONFIG_SYS_IFC_CCR	0x01000000
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
+					 CONFIG_SYS_FLASH_BASE + 0x40000000}
+#endif
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
+				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
+				| CSOR_NAND_PB(128))	/* Pages Per Block 128*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x0e) | \
+					FTIM0_NAND_TWP(0x30)   | \
+					FTIM0_NAND_TWCHT(0x0e) | \
+					FTIM0_NAND_TWH(0x14))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x64) | \
+					FTIM1_NAND_TWBE(0xab)  | \
+					FTIM1_NAND_TRR(0x1c)   | \
+					FTIM1_NAND_TRP(0x30))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x1e) | \
+					FTIM2_NAND_TREH(0x14) | \
+					FTIM2_NAND_TWHRE(0x3c))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
+
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_LBMAP_SWITCH		0x06
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_LBMAP_NAND		0x09
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RST_CTL_RESET_EN		0x30
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_RCW_SRC_NAND		0x119
+#define	QIXIS_RST_FORCE_MEM		0x01
+
+#define CONFIG_SYS_CSPR3_EXT	(0x0)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+
+#define CONFIG_SYS_AMASK3	IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
+					FTIM2_GPCM_TCH(0xf) | \
+					FTIM2_GPCM_TWP(0x3E))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR2_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		(2048 * 1024)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_SPL_PAD_TO		0x80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(1024 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x2000
+#endif
+
+/* Debug Server firmware */
+#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
+#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580D00000ULL
+
+/* MC firmware */
+#define CONFIG_SYS_LS_MC_FW_IN_NOR
+#define CONFIG_SYS_LS_MC_FW_ADDR	0x580300000ULL
+
+#define CONFIG_SYS_LS_MC_DPL_IN_NOR
+#define CONFIG_SYS_LS_MC_DPL_ADDR	0x580700000ULL
+
+#define CONFIG_SYS_LS_MC_DPC_IN_NOR
+#define CONFIG_SYS_LS_MC_DPC_ADDR	0x580800000ULL
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+
+/*
+ * I2C
+ */
+#define I2C_MUX_PCA_ADDR		0x77
+#define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
+
+/* I2C bus multiplexer */
+#define I2C_MUX_CH_DEFAULT      0x8
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231               1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+#define CONFIG_FSL_MEMAC
+#define CONFIG_PCI		/* Enable PCIE */
+#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
+
+#ifdef CONFIG_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_E1000
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*  MMC  */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Initial environment variables */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x80100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0x581100000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x1000000\0"
+
+#endif /* __LS2_RDB_H */
diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index c133ba9..c348d38 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -176,6 +176,7 @@
 #ifdef CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_RTC_BUS_NUM		1 /* I2C2 */
 #endif
 
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index 5999d60..e909623 100644
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -35,7 +35,7 @@
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MVTWSI
-#define CONFIG_I2C_MVTWSI_BASE		MVEBU_TWSI_BASE
+#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
 #define CONFIG_SYS_I2C_SLAVE		0x0
 #define CONFIG_SYS_I2C_SPEED		100000
 
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index f8cd39d..244a9ab 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -42,6 +42,7 @@
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_MXC_SPI
 #define CONFIG_MXC_GPIO
 
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index 9b003fc..7c3dc20 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -48,6 +48,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index fb2072d..22a9fc4 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -41,6 +41,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 
 /* PMIC Configs */
 #define CONFIG_POWER
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 3551e02..a56e72e 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -76,6 +76,7 @@
 /* I2C Configs */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 
 /* PMIC Controller */
 #define CONFIG_POWER
diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
index 3da0ef4..0785491 100644
--- a/include/configs/mx53smd.h
+++ b/include/configs/mx53smd.h
@@ -38,6 +38,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
new file mode 100644
index 0000000..b569f34
--- /dev/null
+++ b/include/configs/mx6cuboxi.h
@@ -0,0 +1,218 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the SolidRun mx6 based boards
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __MX6CUBOXI_CONFIG_H
+#define __MX6CUBOXI_CONFIG_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+#include "mx6_common.h"
+
+#define CONFIG_MX6
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#include "imx6_spl.h"
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_IMX6_THERMAL
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_SYS_MALLOC_LEN		(2 * SZ_1M)
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_GPIO
+#define CONFIG_MXC_UART
+#define CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* Ethernet Configuration */
+#define CONFIG_FEC_MXC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_FEC_MXC_PHYADDR		0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_NO_FLASH
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_SETEXPR
+
+#define CONFIG_BOOTDELAY		1
+
+#define CONFIG_LOADADDR			0x12000000
+#define CONFIG_SYS_TEXT_BASE		0x17800000
+
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+#define CONFIG_CONSOLE_DEV	"ttymxc0"
+#define CONFIG_MMCROOT		"/dev/mmcblk0p2"
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#define CONFIG_SYS_MMC_ENV_DEV		0	/* SDHC2 */
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"fdtfile=undefined\0" \
+	"fdt_addr_r=0x18000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"console=" CONFIG_CONSOLE_DEV "\0" \
+	"bootm_size=0x10000000\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr_r}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
+				"bootz ${loadaddr} - ${fdt_addr_r}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"findfdt="\
+		"if test $board_name = HUMMINGBOARD && test $board_rev = MX6Q ; then " \
+			"setenv fdtfile imx6q-hummingboard.dtb; fi; " \
+		"if test $board_name = HUMMINGBOARD && test $board_rev = MX6DL ; then " \
+			"setenv fdtfile imx6dl-hummingboard.dtb; fi; " \
+		"if test $board_name = CUBOXI && test $board_rev = MX6Q ; then " \
+			"setenv fdtfile imx6q-cubox-i.dtb; fi; " \
+		"if test $board_name = CUBOXI && test $board_rev = MX6DL ; then " \
+			"setenv fdtfile imx6dl-cubox-i.dtb; fi; " \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine dtb to use; fi; \0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"run findfdt; " \
+	"mmc dev ${mmcdev};" \
+	"if mmc rescan; then " \
+		"if run loadbootscript; then " \
+		"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE              256
+#define CONFIG_SYS_MAXARGS             16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_SYS_SDRAM_BASE          MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(8 * 64 * 1024)
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_CACHE
+
+#endif                         /* __MX6CUBOXI_CONFIG_H */
diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h
index 51042ca..2260344 100644
--- a/include/configs/mx6qsabreauto.h
+++ b/include/configs/mx6qsabreauto.h
@@ -56,6 +56,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
 
 /* NAND flash command */
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index 99d9d4d..dab2fd2 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -52,6 +52,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		  100000
 
 /* PMIC */
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index dad49f9..cd023de 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -52,6 +52,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		  100000
 
 /* PMIC */
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index a29d62f..248303c 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -176,6 +176,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		  100000
 
 /* PMIC */
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 8ef4b73..eaa2c2c 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -63,6 +63,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_I2C_EDID
 
@@ -142,6 +143,9 @@
 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (6 * 1024 * 1024)
 #define CONFIG_BMP_16BPP
 #define CONFIG_IPUV3_CLK 260000000
 #define CONFIG_CMD_HDMIDETECT
diff --git a/include/configs/novena.h b/include/configs/novena.h
index 3809c6c..5f83469 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -141,6 +141,7 @@
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_MXC
 #define CONFIG_SYS_I2C_SPEED		100000
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
new file mode 100644
index 0000000..68b4010
--- /dev/null
+++ b/include/configs/omapl138_lcdk.h
@@ -0,0 +1,330 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_USE_SPIFLASH
+#undef	CONFIG_SYS_USE_NOR
+#define	CONFIG_USE_NAND
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_OMAPL138_LCDK
+#define CONFIG_ARM926EJS		/* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
+#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ		24000000
+#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE		0xc1080000
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE	(128 << 20) /* SDRAM size 128MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END 	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
+
+#define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE	(256*1024) /* regular stack */
+
+#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
+	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
+	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
+	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
+	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
+	DAVINCI_SYSCFG_SUSPSRC_I2C)
+
+/*
+ * PLL configuration
+ */
+#define CONFIG_SYS_DV_CLKMODE          0
+#define CONFIG_SYS_DA850_PLL0_POSTDIV  1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
+#define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
+#define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
+#define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
+
+#define CONFIG_SYS_DA850_PLL1_POSTDIV  1
+#define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
+#define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
+#define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8003
+
+#define CONFIG_SYS_DA850_PLL0_PLLM     24
+#define CONFIG_SYS_DA850_PLL1_PLLM     21
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
+#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
+#define CONFIG_SF_DEFAULT_SPEED		30000000
+#define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
+
+#ifdef CONFIG_USE_SPIFLASH
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
+#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x30000
+#endif
+
+/*
+ * I2C Configuration
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED	25000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE	10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C_EXPANDER_ADDR	0x20
+
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
+#define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
+#define CONFIG_ENV_SIZE			(128 << 9)
+#define	CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define	CONFIG_SYS_NAND_PAGE_2K
+#define	CONFIG_SYS_NAND_BUSWIDTH_16_BIT
+#define CONFIG_SYS_NAND_CS		3
+#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_CLE_MASK		0x10
+#define CONFIG_SYS_ALE_MASK		0x8
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS			1
+#endif
+
+#ifdef CONFIG_SYS_USE_NOR
+#define CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ	(128 << 10) /* 128KB */
+#define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ * 3)
+#define CONFIG_ENV_SIZE			(128 << 10)
+#define CONFIG_SYS_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#define PHYS_FLASH_SIZE			(8 << 20) /* Flash size 8MB */
+#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
+	       + 3)
+#define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_FLASH_SECT_SZ
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE			(64 << 10)
+#define CONFIG_ENV_OFFSET		(256 << 10)
+#define CONFIG_ENV_SECT_SIZE		(64 << 10)
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM	7
+#define CONFIG_MII
+#undef	CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#define CONFIG_NET_MULTI
+#endif
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOOTFILE		"uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT	"U-Boot > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS		"console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootwait ip=off"
+#define CONFIG_BOOTCOMMAND	"if mmc rescan 0; then if fatload mmc 0 0xc0600000 boot.scr; then source 0xc0600000; else fatload mmc 0 0xc0700000 uImage; bootm c0700000; fi; else sf probe 0; sf read 0xc0700000 0x80000 0x220000; bootm 0xc0700000; fi"
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SAVEENV
+#endif
+
+#if !defined(CONFIG_USE_NAND) && \
+	!defined(CONFIG_SYS_USE_NOR) && \
+	!defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE		(16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ENV
+#endif
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DAVINCI_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+#undef CONFIG_ENV_IS_IN_MMC
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_SIZE
+#undef CONFIG_ENV_OFFSET
+#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
+#define CONFIG_ENV_OFFSET	(51 << 9)	/* Sector 51 */
+#undef CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_ENV_IS_IN_NAND
+#undef CONFIG_ENV_IS_IN_SPI_FLASH
+#endif
+
+#ifndef CONFIG_DIRECT_NOR_BOOT
+/* defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE - \
+						CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LDSCRIPT	"board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
+#define CONFIG_SPL_STACK	0x8001ff00
+#define CONFIG_SPL_TEXT_BASE	0x80000000
+#define CONFIG_SPL_MAX_FOOTPRINT	32768
+#define CONFIG_SPL_PAD_TO	32768
+#endif
+
+/* additions for new relocation code, must added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0xc0000000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
+					GENERATED_GBL_DATA_SIZE)
+#endif /* __CONFIG_H */
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index 3c60b4f..200f40a 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -62,6 +62,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED            100000
 
 /* OCOTP Configs */
diff --git a/include/configs/platinum.h b/include/configs/platinum.h
index 134bb45..91ffc7c 100644
--- a/include/configs/platinum.h
+++ b/include/configs/platinum.h
@@ -62,6 +62,7 @@
 /* I2C config */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED			100000
 
 /* MMC config */
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
index 763a47a..7071849 100644
--- a/include/configs/qemu-ppce500.h
+++ b/include/configs/qemu-ppce500.h
@@ -50,8 +50,14 @@
 /* Physical address should be a function call */
 #ifndef __ASSEMBLY__
 extern unsigned long long get_phys_ccsrbar_addr_early(void);
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32)
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early()
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
 #endif
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+
+#define CONFIG_PHYS_64BIT
 
 /* Virtual address range for PCI region maps */
 #define CONFIG_SYS_PCI_MAP_START	0x80000000
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index febbfb6..3bf45a2 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -21,9 +21,6 @@
 
 #define CONFIG_SYS_TIMER_RATE		1000000
 
-#define CONFIG_BOOTSTAGE
-#define CONFIG_BOOTSTAGE_REPORT
-
 #define CONFIG_SYS_STDIO_DEREGISTER
 
 /* Number of bits in a C 'long' on this architecture */
@@ -34,6 +31,10 @@
 #define CONFIG_CMD_FDT
 #define CONFIG_ANDROID_BOOT_IMAGE
 
+#define CONFIG_CMD_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_CMD_IO
+
 #define CONFIG_FS_FAT
 #define CONFIG_FAT_WRITE
 #define CONFIG_FS_EXT4
@@ -47,15 +48,12 @@
 #define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_MD5SUM
 
-#define CONFIG_SYS_VSNPRINTF
-
 #define CONFIG_CMD_GPIO
-#define CONFIG_SANDBOX_GPIO
-#define CONFIG_SANDBOX_GPIO_COUNT	128
 
 #define CONFIG_CMD_GPT
 #define CONFIG_PARTITION_UUIDS
 #define CONFIG_EFI_PARTITION
+#define CONFIG_DOS_PARTITION
 
 /*
  * Size of malloc() pool, before and after relocation
@@ -75,13 +73,11 @@
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_COMMAND_HISTORY
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_ENV_SIZE		8192
 #define CONFIG_ENV_IS_NOWHERE
 
 /* SPI - enable all SPI flash types for testing purposes */
-#define CONFIG_SANDBOX_SPI
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SF_TEST
 #define CONFIG_CMD_SPI
@@ -90,14 +86,12 @@
 #define CONFIG_SPI_FLASH_EON
 #define CONFIG_SPI_FLASH_GIGADEVICE
 #define CONFIG_SPI_FLASH_MACRONIX
-#define CONFIG_SPI_FLASH_SANDBOX
 #define CONFIG_SPI_FLASH_SPANSION
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_SPI_FLASH_WINBOND
 
 #define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_SANDBOX
 #define CONFIG_I2C_EDID
 #define CONFIG_I2C_EEPROM
 
@@ -125,29 +119,42 @@
 
 /* include default commands */
 #include <config_cmd_default.h>
-
-/* We don't have networking support yet */
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
+#include <config_distro_defaults.h>
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(HOST, host, 1) \
+	func(HOST, host, 0)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_KEEP_SERVERADDR
+#define CONFIG_UDP_CHECKSUM
+#define CONFIG_CMD_LINK_LOCAL
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DNS
+#define CONFIG_CMD_SNTP
+#define CONFIG_TIMESTAMP
+#define CONFIG_CMD_RARP
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_SERVERIP
+#define CONFIG_IP_DEFRAG
+
+/* Can't boot elf images */
+#undef CONFIG_CMD_ELF
 
 #define CONFIG_CMD_HASH
 #define CONFIG_HASH_VERIFY
 #define CONFIG_SHA1
 #define CONFIG_SHA256
 
-#define CONFIG_TPM_TIS_SANDBOX
-
 #define CONFIG_CMD_SANDBOX
 
 #define CONFIG_BOOTARGS ""
 
-#define CONFIG_ARCH_EARLY_INIT_R
 #define CONFIG_BOARD_LATE_INIT
 
-#define CONFIG_SOUND
-#define CONFIG_SOUND_SANDBOX
-#define CONFIG_CMD_SOUND
-
 #ifndef SANDBOX_NO_SDL
 #define CONFIG_SANDBOX_SDL
 #endif
@@ -165,23 +172,40 @@
 
 #define CONFIG_KEYBOARD
 
-#define CONFIG_EXTRA_ENV_SETTINGS	"stdin=serial,cros-ec-keyb\0" \
+#define SANDBOX_SERIAL_SETTINGS		"stdin=serial,cros-ec-keyb\0" \
 					"stdout=serial,lcd\0" \
 					"stderr=serial,lcd\0"
 #else
-
-#define CONFIG_EXTRA_ENV_SETTINGS	"stdin=serial\0" \
+#define SANDBOX_SERIAL_SETTINGS		"stdin=serial\0" \
 					"stdout=serial,lcd\0" \
 					"stderr=serial,lcd\0"
 #endif
 
+#define SANDBOX_ETH_SETTINGS		"ethaddr=00:00:11:22:33:44\0" \
+					"eth1addr=00:00:11:22:33:45\0" \
+					"eth5addr=00:00:11:22:33:46\0" \
+					"ipaddr=1.2.3.4\0"
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"kernel_addr_r=0x1000000\0" \
+	"fdt_addr_r=0xc00000\0" \
+	"ramdisk_addr_r=0x2000000\0" \
+	"scriptaddr=0x1000\0" \
+	"pxefile_addr_r=0x2000\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	SANDBOX_SERIAL_SETTINGS \
+	SANDBOX_ETH_SETTINGS \
+	BOOTENV \
+	MEM_LAYOUT_ENV_SETTINGS
+
 #define CONFIG_GZIP_COMPRESSED
 #define CONFIG_BZIP2
 #define CONFIG_LZO
 #define CONFIG_LZMA
 
-#define CONFIG_TPM_TIS_SANDBOX
-
 #define CONFIG_CMD_LZMADEC
+#define CONFIG_CMD_USB
 
 #endif
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
index 3b06d30..08381e3 100644
--- a/include/configs/smdk5250.h
+++ b/include/configs/smdk5250.h
@@ -22,7 +22,6 @@
 #define CONFIG_POWER_MAX77686
 
 #define CONFIG_BOARD_COMMON
-#define CONFIG_ARCH_EARLY_INIT_R
 
 #define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_EXYNOS
diff --git a/include/configs/snow.h b/include/configs/snow.h
index fe802f2..a2fb3f9 100644
--- a/include/configs/snow.h
+++ b/include/configs/snow.h
@@ -23,10 +23,11 @@
 #define CONFIG_POWER_TPS65090_I2C
 
 #define CONFIG_BOARD_COMMON
-#define CONFIG_ARCH_EARLY_INIT_R
 
 #define CONFIG_USB_XHCI
+#define CONFIG_USB_EHCI
 #define CONFIG_USB_XHCI_EXYNOS
+#define CONFIG_USB_EHCI_EXYNOS
 
 #define CONFIG_SYS_PROMPT		"snow # "
 #define CONFIG_IDENT_STRING		" for snow"
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 6d93472..41bb52b 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -40,7 +40,7 @@
 #define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
 
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000 - 0x100)
+#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000 - CONFIG_SYS_SPL_MALLOC_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR					\
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE -	\
 	GENERATED_GBL_DATA_SIZE)
@@ -99,7 +99,6 @@
  * Ethernet on SoC (EMAC)
  */
 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-#define CONFIG_DESIGNWARE_ETH
 #define CONFIG_NET_MULTI
 #define CONFIG_DW_ALTDESCRIPTOR
 #define CONFIG_MII
@@ -293,6 +292,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SYS_SPL_MALLOC_START	CONFIG_SYS_INIT_SP_ADDR
 #define CONFIG_SYS_SPL_MALLOC_SIZE	(5 * 1024)
+#define CONFIG_SPL_MAX_SIZE		(64 * 1024)
 
 #define CHUNKSZ_CRC32			(1 * 1024)	/* FIXME: ewww */
 #define CONFIG_CRC32_VERIFY
@@ -305,6 +305,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SPL_WATCHDOG_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 
+/*
+ * Stack setup
+ */
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+
 #ifdef CONFIG_SPL_BUILD
 #undef CONFIG_PARTITIONS
 #endif
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 16281f5..409cf54 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -18,7 +18,6 @@
 
 /* Ethernet driver configuration */
 #define CONFIG_MII
-#define CONFIG_DESIGNWARE_ETH
 #define CONFIG_NET_MULTI
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h
new file mode 100644
index 0000000..7f569fd
--- /dev/null
+++ b/include/configs/stm32f429-discovery.h
@@ -0,0 +1,106 @@
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_STM32F4
+#define CONFIG_STM32F4DISCOVERY
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_FLASH_BASE		0x08000000
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x10010000
+#define CONFIG_SYS_TEXT_BASE		0x08000000
+
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Configuration of the external SDRAM memory
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_RAM_SIZE		(8 << 20)
+#define CONFIG_SYS_RAM_CS		1
+#define CONFIG_SYS_RAM_FREQ_DIV		2
+#define CONFIG_SYS_RAM_BASE		0xD0000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_RAM_BASE
+#define CONFIG_SYS_LOAD_ADDR		0xD0400000
+#define CONFIG_LOADADDR			0xD0400000
+
+#define CONFIG_SYS_MAX_FLASH_SECT	12
+#define CONFIG_SYS_MAX_FLASH_BANKS	2
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET		(256 << 10)
+#define CONFIG_ENV_SECT_SIZE		(128 << 10)
+#define CONFIG_ENV_SIZE			(8 << 10)
+
+#define CONFIG_BOARD_SPECIFIC_LED
+#define CONFIG_RED_LED			110
+#define CONFIG_GREEN_LED		109
+
+#define CONFIG_STM32_GPIO
+#define CONFIG_STM32_SERIAL
+
+#define CONFIG_STM32_USART1
+
+#define CONFIG_STM32_HSE_HZ		8000000
+
+#define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_SYS_MAXARGS		16
+
+#define CONFIG_SYS_MALLOC_LEN		(2 << 20)
+
+#define CONFIG_STACKSIZE		(64 << 10)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTARGS							\
+	"console=ttystm0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+#define CONFIG_BOOTCOMMAND						\
+	"run bootcmd_romfs"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
+	"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
+	"bootm 0x08044000 - 0x08042000\0"
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_AUTOBOOT
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT	       "U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MEM
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_TIMER
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index 156e0fa..ab1e61c 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@@ -55,7 +55,6 @@
 #define CONFIG_MII
 #define CONFIG_PHYLIB
 #define CONFIG_CMD_NET
-#define CONFIG_DESIGNWARE_ETH
 #define CONFIG_DW_ALTDESCRIPTOR
 #define CONFIG_PHY_MICREL
 
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 1f7a1cb..365d9a5 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -196,7 +196,11 @@
 #endif
 
 #define CONFIG_SYS_I2C
+#if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \
+    defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \
+    defined CONFIG_I2C4_ENABLE
 #define CONFIG_SYS_I2C_MVTWSI
+#endif
 #define CONFIG_SYS_I2C_SPEED		400000
 #define CONFIG_SYS_I2C_SLAVE		0x7f
 
@@ -284,7 +288,6 @@ extern int soft_i2c_gpio_scl;
 #endif
 
 #ifdef CONFIG_SUNXI_GMAC
-#define CONFIG_DESIGNWARE_ETH		/* GMAC can use designware driver */
 #define CONFIG_DW_AUTONEG
 #define CONFIG_PHY_GIGE			/* GMAC can use gigabit PHY	*/
 #define CONFIG_PHY_ADDR		1
diff --git a/include/configs/tb100.h b/include/configs/tb100.h
index 501449a..b2b4b10 100644
--- a/include/configs/tb100.h
+++ b/include/configs/tb100.h
@@ -62,7 +62,6 @@
 /*
  * Ethernet configuration
  */
-#define CONFIG_DESIGNWARE_ETH
 #define ETH0_BASE_ADDRESS		0xFE100000
 #define ETH1_BASE_ADDRESS		0xFE110000
 
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index 7089378..3a88f22 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -199,6 +199,7 @@
 #ifdef CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_I2C_EDID
 #endif
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 7957a73..f2be8d5 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -144,13 +144,20 @@
 	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
 	DFUARGS \
 
+
 #define CONFIG_BOOTCOMMAND \
+	"if test ${dofastboot} -eq 1; then " \
+		"echo Boot fastboot requested, resetting dofastboot ...;" \
+		"setenv dofastboot 0; saveenv;" \
+		"echo Booting into fastboot ...; fastboot;" \
+	"fi;" \
 	"run findfdt; " \
 	"run mmcboot;" \
 	"setenv mmcdev 1; " \
 	"setenv bootpart 1:2; " \
 	"setenv mmcroot /dev/mmcblk0p2 rw; " \
 	"run mmcboot;" \
+	""
 
 
 /*
diff --git a/include/configs/titanium.h b/include/configs/titanium.h
index f9e00c5..320d76c 100644
--- a/include/configs/titanium.h
+++ b/include/configs/titanium.h
@@ -44,6 +44,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
 
 /* MMC Configs */
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index a099687..012fa1c 100644
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@@ -35,16 +35,6 @@
 #define PHYS_SDRAM_SIZE			(1024u * SZ_1M)
 #endif
 
-#if defined(CONFIG_MBA6)
-
-#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
-#define CONFIG_DEFAULT_FDT_FILE		"imx6dl-mba6x.dtb"
-#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q)
-#define CONFIG_DEFAULT_FDT_FILE		"imx6q-mba6x.dtb"
-#endif
-
-#endif
-
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_SYS_GENERIC_BOARD
@@ -80,16 +70,12 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_SYS_I2C_SPEED		100000
 
 /* I2C SYSMON (LM75) */
 #define CONFIG_DTT_LM75
-#if defined(CONFIG_MBA6)
-#define CONFIG_DTT_SENSORS		{ 0, 1 }
-#else
-#define CONFIG_DTT_SENSORS		{ 0 }
-#endif
 #define CONFIG_DTT_MAX_TEMP		70
 #define CONFIG_DTT_MIN_TEMP		-30
 #define CONFIG_DTT_HYSTERESIS	3
@@ -147,38 +133,12 @@
 #define CONFIG_PHYLIB
 #define CONFIG_MII
 
-#if defined(CONFIG_MBA6)
-
-#define CONFIG_FEC_XCV_TYPE		RGMII
-#define CONFIG_ETHPRIME			"FEC"
-
-#define CONFIG_FEC_MXC_PHYADDR		0x03
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_KSZ9031
-
-#else
-
-#error "define PHY to use for your baseboard"
-
-#endif
-
 #define CONFIG_ARP_TIMEOUT		200UL
 /* Network config - Allow larger/faster download for TFTP/NFS */
 #define CONFIG_IP_DEFRAG
 #define CONFIG_TFTP_BLOCKSIZE	4096
 #define CONFIG_NFS_READ_SIZE	4096
 
-#if defined(CONFIG_MBA6)
-
-#define CONFIG_MXC_UART_BASE		UART2_BASE
-#define CONFIG_CONSOLE_DEV		"ttymxc1"
-
-#else
-
-#error "define baseboard specific things (uart, number of SD-card slots)"
-
-#endif
-
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX		1
@@ -492,4 +452,20 @@
 #define CONFIG_CMD_CACHE
 #endif
 
+/*
+ * All the defines above are for the TQMa6 SoM
+ *
+ * Now include the baseboard specific configuration
+ */
+#ifdef CONFIG_MBA6
+#include "tqma6_mba6.h"
+#else
+#error "No baseboard for the TQMa6 defined!"
+#endif
+
+/* Support at least the sensor on TQMa6 SOM */
+#if !defined(CONFIG_DTT_SENSORS)
+#define CONFIG_DTT_SENSORS		{ 0 }
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h
new file mode 100644
index 0000000..88c0067
--- /dev/null
+++ b/include/configs/tqma6_mba6.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
+ *
+ * Configuration settings for the TQ Systems TQMa6<Q,S> module.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_TQMA6_MBA6_H
+#define __CONFIG_TQMA6_MBA6_H
+
+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#define CONFIG_DEFAULT_FDT_FILE		"imx6dl-mba6x.dtb"
+#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q)
+#define CONFIG_DEFAULT_FDT_FILE		"imx6q-mba6x.dtb"
+#endif
+
+#define CONFIG_DTT_SENSORS		{ 0, 1 }
+
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+
+#define CONFIG_FEC_MXC_PHYADDR		0x03
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_KSZ9031
+
+#define CONFIG_MXC_UART_BASE		UART2_BASE
+#define CONFIG_CONSOLE_DEV		"ttymxc1"
+
+#endif /* __CONFIG_TQMA6_MBA6_H */
diff --git a/include/configs/tseries.h b/include/configs/tseries.h
index a6c7d5f..1e41a12 100644
--- a/include/configs/tseries.h
+++ b/include/configs/tseries.h
@@ -23,6 +23,8 @@
 #define CONFIG_HW_WATCHDOG
 #define CONFIG_OMAP_WATCHDOG
 #define CONFIG_SPL_WATCHDOG_SUPPORT
+
+#define CONFIG_SPL_GPIO_SUPPORT
 /* Bootcount using the RTC block */
 #define CONFIG_SYS_BOOTCOUNT_ADDR	0x44E3E000
 #define CONFIG_BOOTCOUNT_LIMIT
@@ -103,15 +105,16 @@
 	"mtdparts=" MTDPARTS_DEFAULT "\0" \
 	"nandargs=setenv bootargs console=${console} " \
 		"${optargs} " \
-		"root=${nandroot} " \
-		"rootfstype=${nandrootfstype}\0" \
-	"nandroot=ubi0:rootfs rw ubi.mtd=8,2048\0" \
-	"nandrootfstype=ubifs rootwait=1\0" \
-	"nandimgsize=0x500000\0" \
-	"nandboot=echo Booting from nand ...; " \
+		"root=mtd6 " \
+		"rootfstype=jffs2\0" \
+	"kernelsize=0x400000\0" \
+	"nandboot=echo booting from nand ...; " \
 		"run nandargs; " \
-		"nand read ${loadaddr} kernel ${nandimgsize}; " \
-		"bootz ${loadaddr}\0"
+		"nand read ${loadaddr} kernel ${kernelsize}; " \
+		"bootz ${loadaddr} - ${dtbaddr}\0" \
+	"defboot=run nandboot\0" \
+	"bootlimit=1\0" \
+	"altbootcmd=run usbscript\0"
 #else
 #define NANDARGS ""
 #endif /* CONFIG_NAND */
@@ -231,15 +234,15 @@ MMCARGS
 
 #define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
 #define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:" \
-					"128k(SPL)," \
-					"128k(SPL.backup1)," \
-					"128k(SPL.backup2)," \
-					"128k(SPL.backup3)," \
-					"512k(u-boot)," \
-					"128k(u-boot-spl-os)," \
+					"128k(MLO)," \
+					"128k(MLO.backup)," \
+					"128k(dtb)," \
 					"128k(u-boot-env)," \
-					"5m(kernel),"\
-					"-(rootfs)"
+					"512k(u-boot)," \
+					"4m(kernel),"\
+					"128m(rootfs),"\
+					"-(user)"
+#define CONFIG_NAND_OMAP_GPMC_WSCFG	1
 #endif /* CONFIG_NAND */
 
 /* USB configuration */
@@ -298,7 +301,7 @@ MMCARGS
 #else
 #define CONFIG_ENV_IS_IN_NAND
 #endif
-#define CONFIG_ENV_OFFSET		0x120000 /* TODO: Adresse definieren */
+#define CONFIG_ENV_OFFSET		0x60000
 #define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_ENV_SIZE
 #else
 #error "no storage for Environment defined!"
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index 3fda20a..032010b 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -8,10 +8,9 @@
 #ifndef __VEXPRESS_AEMV8A_H
 #define __VEXPRESS_AEMV8A_H
 
-#define CONFIG_DM
-
-/* We use generic board for v8 Versatile Express */
+/* We use generic board and device manager for v8 Versatile Express */
 #define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DM
 
 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
 #ifndef CONFIG_SEMIHOSTING
@@ -134,27 +133,16 @@
 #endif
 
 /* PL011 Serial Configuration */
-#define CONFIG_BAUDRATE			115200
-#ifdef CONFIG_DM
 #define CONFIG_DM_SERIAL
-#define CONFIG_PL01X_SERIAL
-#else
-#define CONFIG_SYS_SERIAL0		V2M_UART0
-#define CONFIG_SYS_SERIAL1		V2M_UART1
+#define CONFIG_BAUDRATE			115200
 #define CONFIG_CONS_INDEX		0
+#define CONFIG_PL01X_SERIAL
 #define CONFIG_PL011_SERIAL
 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
 #define CONFIG_PL011_CLOCK		7273800
 #else
 #define CONFIG_PL011_CLOCK		24000000
 #endif
-#define CONFIG_PL01x_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
-					 (void *)CONFIG_SYS_SERIAL1}
-#endif
-
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_SERIAL0		V2M_UART0
-#define CONFIG_SYS_SERIAL1		V2M_UART1
 
 /* Command line configuration */
 #define CONFIG_MENU
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index b586803..b2c3614 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -62,6 +62,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
 
 /* MMC Configuration */
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
index 48b8692..d0895cf 100644
--- a/include/configs/woodburn_common.h
+++ b/include/configs/woodburn_common.h
@@ -47,6 +47,7 @@
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_SPD_BUS_NUM		0
 #define CONFIG_MXC_SPI
 #define CONFIG_MXC_GPIO
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 241bf65..27a66a5 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -74,7 +74,6 @@
 
 /* Ethernet config options */
 #define CONFIG_MII
-#define CONFIG_DESIGNWARE_ETH
 #define CONFIG_NET_MULTI
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
new file mode 100644
index 0000000..b6a76fe
--- /dev/null
+++ b/include/configs/x86-chromebook.h
@@ -0,0 +1,68 @@
+/*
+ *
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _X86_CHROMEBOOK_H
+#define _X86_CHROMEBOOK_H
+
+#define CONFIG_SYS_MONITOR_LEN			(1 << 20)
+
+#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE		0x4000
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_NR_DRAM_BANKS			8
+#define CONFIG_X86_MRC_ADDR			0xfffa0000
+#define CONFIG_CACHE_MRC_SIZE_KB		512
+
+#define CONFIG_X86_SERIAL
+
+#define CONFIG_SCSI_DEV_LIST	\
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}
+
+#define CONFIG_X86_OPTION_ROM_FILE		pci8086,0166.bin
+#define CONFIG_X86_OPTION_ROM_ADDR		0xfff90000
+
+#define CONFIG_PCI_MEM_BUS	0xe0000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_PREF_BUS	0xd0000000
+#define CONFIG_PCI_PREF_PHYS	CONFIG_PCI_PREF_BUS
+#define CONFIG_PCI_PREF_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x1000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0xefff
+
+#define CONFIG_SYS_EARLY_PCI_INIT
+#define CONFIG_PCI_PNP
+
+#define CONFIG_BIOSEMU
+#define VIDEO_IO_OFFSET				0
+#define CONFIG_X86EMU_RAW_IO
+
+#define CONFIG_CROS_EC
+#define CONFIG_CROS_EC_LPC
+#define CONFIG_CMD_CROS_EC
+#define CONFIG_ARCH_EARLY_INIT_R
+
+#undef CONFIG_ENV_IS_NOWHERE
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET		0x003f8000
+
+#define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,serial\0" \
+					"stdout=vga,serial\0" \
+					"stderr=vga,serial\0"
+
+#endif
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index b7dd63e..9571c65 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -16,7 +16,6 @@
  * (easy to change)
  */
 #define CONFIG_SHOW_BOOT_PROGRESS
-#define CONFIG_SYS_VSNPRINTF
 #define CONFIG_ZBOOT_32
 #define CONFIG_PHYSMEM
 #define CONFIG_DISPLAY_BOARDINFO_LATE
@@ -204,7 +203,6 @@
 #define CONFIG_CMD_SF_TEST
 #define CONFIG_CMD_SPI
 #define CONFIG_SPI
-#define CONFIG_OF_SPI_FLASH
 
 /*-----------------------------------------------------------------------
  * Environment configuration
@@ -238,9 +236,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-#define CONFIG_BOOTSTAGE
-#define CONFIG_CMD_BOOTSTAGE
-
 #define CONFIG_CMD_USB
 
 /* Default environment */
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 511ecca..880d29c 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -36,7 +36,7 @@
 #define CPU_RELEASE_ADDR	0xFFFFFF0
 
 /* Cache Definitions */
-#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_CACHELINE_SIZE	64
 
 #define CONFIG_IDENT_STRING		" Xilinx ZynqMP"
 
@@ -61,13 +61,25 @@
 #define CONFIG_SYS_BAUDRATE_TABLE \
 	{ 4800, 9600, 19200, 38400, 57600, 115200 }
 
+#define CONFIG_ZYNQ_SDHCI0
+
 /* Command line configuration */
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_MEMORY
 #define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_ELF
+#define CONFIG_MP
+
+/* SPI */
+#ifdef CONFIG_ZYNQ_SPI
+# define CONFIG_SPI_FLASH
+# define CONFIG_SPI_FLASH_SST
+# define CONFIG_CMD_SF
+#endif
 
 #if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
 # define CONFIG_MMC
@@ -90,8 +102,8 @@
 	"kernel_addr=0x80000\0" \
 	"fdt_addr=0x7000000\0" \
 	"fdt_high=0x10000000\0" \
-	"sdboot=mmcinfo && fatload mmc 0:0 $fdt_addr system.dtb && " \
-		"fatload mmc 0:0 $kernel_addr Image && booti $kernel_addr - $fdt_addr\0"
+	"sdboot=mmcinfo && load mmc 0:0 $fdt_addr system.dtb && " \
+		"load mmc 0:0 $kernel_addr Image && booti $kernel_addr - $fdt_addr\0"
 
 #define CONFIG_BOOTARGS		"setenv bootargs console=ttyPS0,${baudrate} " \
 				"earlycon=cdns,mmio,0xff000000,${baudrate}n8"
@@ -117,6 +129,29 @@
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SYS_MAXARGS		64
 
+#define CONFIG_ZYNQ_I2C0
+#define CONFIG_SYS_I2C_ZYNQ
+
+/* I2C */
+#if defined(CONFIG_SYS_I2C_ZYNQ)
+# define CONFIG_CMD_I2C
+# define CONFIG_SYS_I2C
+# define CONFIG_SYS_I2C_ZYNQ_SPEED		100000
+# define CONFIG_SYS_I2C_ZYNQ_SLAVE		0
+#endif
+
+#define CONFIG_ZYNQMP_EEPROM
+
+/* EEPROM */
+#ifdef CONFIG_ZYNQMP_EEPROM
+# define CONFIG_CMD_EEPROM
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+# define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
+# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+# define CONFIG_SYS_EEPROM_SIZE			(64 * 1024)
+#endif
+
 #define CONFIG_FIT
 #define CONFIG_FIT_VERBOSE       /* enable fit_format_{error,warning}() */
 
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index a7c6dce..926b381 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -38,6 +38,9 @@
 # define CONFIG_ZYNQ_SERIAL
 #endif
 
+#define CONFIG_ZYNQ_GPIO
+#define CONFIG_CMD_GPIO
+
 /* Ethernet driver */
 #if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1)
 # define CONFIG_NET_MULTI
@@ -290,7 +293,7 @@
 # define CONFIG_SYS_MMC_MAX_DEVICE	1
 #endif
 
-#define CONFIG_SYS_LDSCRIPT  "arch/arm/cpu/armv7/zynq/u-boot.lds"
+#define CONFIG_SYS_LDSCRIPT  "arch/arm/mach-zynq/u-boot.lds"
 
 /* Commands */
 #include <config_cmd_default.h>
@@ -308,7 +311,7 @@
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_BOARD_INIT
 
-#define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/armv7/zynq/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT	"arch/arm/mach-zynq/u-boot-spl.lds"
 
 /* MMC support */
 #ifdef CONFIG_ZYNQ_SDHCI0
diff --git a/include/configs/zynq_picozed.h b/include/configs/zynq_picozed.h
new file mode 100644
index 0000000..d116e05
--- /dev/null
+++ b/include/configs/zynq_picozed.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2015 Xilinx, Inc.
+ *
+ * Configuration for PicoZed
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_PICOZED_H
+#define __CONFIG_ZYNQ_PICOZED_H
+
+#define CONFIG_SYS_SDRAM_SIZE		(1024 * 1024 * 1024)
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0	0
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_SDHCI1
+#define CONFIG_ZYNQ_USB
+#define CONFIG_ZYNQ_BOOT_FREEBSD
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_PICOZED_H */
author	Albert ARIBAUD <albert.u.boot@aribaud.net>	2015-05-05 10:09:06 +0200
committer	Albert ARIBAUD <albert.u.boot@aribaud.net>	2015-05-05 10:09:06 +0200
commit	b939689c7b87773c44275a578ffc8674a867e39d (patch)
tree	785d71eb0bbc707385e4456a14b21706223d99a3 /include/configs
parent	97840b5d1fe0960134c3553a9d9d1c1cd1be784d (diff)
parent	ace97d26176a3ebc9ec07738450de93eea35975c (diff)
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