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authorPaul Kocialkowski <contact@paulk.fr>2015-05-16 19:52:11 +0200
committerHans de Goede <hdegoede@redhat.com>2015-05-19 18:46:44 +0200
commit8a65f69c9cef09aebc20aca98a4ddbf2b4829995 (patch)
treecb822d4355a80482aca76e1845a43525fd6be375 /include/configs
parent5bfdca0d4cebab34d3b81a4a8852d9ec3923b0b9 (diff)
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sunxi: Cache line size definition
Sunxi platforms use ARM Cortex A8, A7 and A15 (unsupported yet) CPU cores, which all have 64 bytes cache line size. This is required to e.g. enable USB gadget. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'include/configs')
-rw-r--r--include/configs/sunxi-common.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index f80f006..d829899 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -66,6 +66,9 @@
# define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE
#endif
+/* CPU */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
/* DRAM Base */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_INIT_RAM_ADDR 0x0