Merge branch 'master' of /home/stefan/git/u-boot/u-boot

6 files changed, 196 insertions, 8 deletions

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 37e3ca4..8705838 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -355,7 +355,6 @@
 
 /* SPI */
 #define CONFIG_MPC8XXX_SPI
-#define CONFIG_HARD_SPI			/* SPI with hardware support */
 #undef CONFIG_SOFT_SPI			/* SPI bit-banged */
 
 /* GPIOs.  Used as SPI chip selects */
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index 349ca14..b412655 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -27,7 +27,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define MV_VERSION  "v1.0.1"
+#include <version.h>
 
 /*
  * High Level Configuration Options
@@ -262,7 +262,7 @@
 #define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR+CFG_ENV_SIZE)
 #define CFG_ENV_SIZE_REDUND 	CFG_ENV_SIZE
 
-#define CONFIG_LOADS_ECHO 
+#define CONFIG_LOADS_ECHO
 #define CFG_LOADS_BAUD_CHANGE
 
 /*
@@ -336,6 +336,7 @@
 #define CFG_HID0_FINAL	CFG_HID0_INIT
 
 #define CFG_HID2	HID2_HBE
+#define CONFIG_HIGH_BATS	1
 
 /* DDR  */
 #define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
@@ -446,7 +447,7 @@
 	"mv_dtb_addr=" MV_DTB_ADDR "\0"				\
 	"mv_dtb_addr_ram=" MV_DTB_ADDR_RAM "\0"			\
 	"dtb_name=" MV_DTB_NAME "\0"				\
-	"mv_version=" MV_VERSION "\0"				\
+	"mv_version=" U_BOOT_VERSION "\0"			\
 	"dhcp_client_id=" MV_CI "\0"				\
 	"dhcp_vendor-class-identifier=" MV_VCI "\0"		\
 	"netretry=no\0"						\
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 3fc9975..7ac51b5 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -114,6 +114,8 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MMC
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
 
 #undef CONFIG_CMD_AUTOSCRIPT
 #undef CONFIG_CMD_FPGA
@@ -126,6 +128,10 @@
 #define CFG_NR_PIOS			5
 #define CFG_HSDRAMC			1
 #define CONFIG_MMC			1
+#define CONFIG_ATMEL_SPI		1
+
+#define CONFIG_SPI_FLASH		1
+#define CONFIG_SPI_FLASH_ATMEL		1
 
 #define CFG_DCACHE_LINESZ		32
 #define CFG_ICACHE_LINESZ		32
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
new file mode 100644
index 0000000..41a6763
--- /dev/null
+++ b/include/configs/davinci_sffsdr.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*=======*/
+/* Board */
+/*=======*/
+#define SFFSDR
+#define CFG_NAND_LARGEPAGE
+#define CFG_USE_NAND
+/*===================*/
+/* SoC Configuration */
+/*===================*/
+#define CONFIG_ARM926EJS			/* arm926ejs CPU core */
+#define CONFIG_SYS_CLK_FREQ	297000000	/* Arm Clock frequency */
+#define CFG_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CFG_HZ_CLOCK		27000000	/* Timer Input clock freq */
+#define CFG_HZ			1000
+/*==================================================*/
+/* EEPROM definitions for Atmel 24LC64 EEPROM chip  */
+/*==================================================*/
+#define CFG_I2C_EEPROM_ADDR_LEN		2
+#define CFG_I2C_EEPROM_ADDR		0x50
+#define CFG_EEPROM_PAGE_WRITE_BITS	5
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+/*=============*/
+/* Memory Info */
+/*=============*/
+#define CFG_MALLOC_LEN		(0x10000 + 256*1024)	/* malloc() len */
+#define CFG_GBL_DATA_SIZE	128		/* reserved for initial data */
+#define CFG_MEMTEST_START	0x80000000	/* memtest start address */
+#define CFG_MEMTEST_END		0x81000000	/* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE	(256*1024)	/* regular stack */
+#define PHYS_SDRAM_1		0x80000000	/* DDR Start */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* DDR size 128MB */
+#define DDR_4BANKS				/* 4-bank DDR2 (128MB) */
+/*====================*/
+/* Serial Driver info */
+/*====================*/
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	4		/* NS16550 register size */
+#define CFG_NS16550_COM1	0x01c20000	/* Base address of UART0 */
+#define CFG_NS16550_CLK		27000000	/* Input clock to NS16550 */
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+/*===================*/
+/* I2C Configuration */
+/*===================*/
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CFG_I2C_SPEED		80000	/* 100Kbps won't work, silicon bug */
+#define CFG_I2C_SLAVE		10	/* Bogus, master-only in U-Boot */
+/*==================================*/
+/* Network & Ethernet Configuration */
+/*==================================*/
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_NO_FLASH
+#define CFG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
+#define CFG_ENV_SECT_SIZE	2048	/* Env sector Size */
+#define CFG_ENV_SIZE		SZ_128K
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
+#define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
+#define CFG_NAND_BASE		0x02000000
+#define CFG_NAND_HW_ECC
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
+#define NAND_MAX_CHIPS		1
+#define CFG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
+/*=====================*/
+/* Board related stuff */
+/*=====================*/
+/*==========================================*/
+/* I2C switch definitions for PCA9543 chip  */
+/* on Lyrtech SFF SDR board.                */
+/* This chip has a single register.         */
+/*==========================================*/
+#define CFG_I2C_PCA9543_ADDR		0x70
+#define CFG_I2C_PCA9543_ADDR_LEN	0
+#define CFG_I2C_PCA9543_ENABLE_CH0	0x01	/* Enable channel 0. */
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+#undef CONFIG_USE_IRQ                  /* No IRQ/FIQ in U-Boot */
+#define CONFIG_MISC_INIT_R
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
+#define CFG_PROMPT		"U-Boot > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		1024		/* Console I/O Buffer Size  */
+/* Print buffer size */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR		0x80700000	/* Default Linux kernel
+						 * load address. */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE		/* Won't work with hush so far,
+					 * may be later */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_CMDLINE_EDITING
+#define CFG_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+/*
+ * Define this to load an Integrity kernel.
+ *
+#define CONFIG_CMD_ELF
+ */
+
+/*===================*/
+/* Linux Information */
+/*===================*/
+#define LINUX_BOOT_PARAM_ADDR	0x80000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS							\
+	"mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND	"setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot"
+
+/*=================*/
+/* U-Boot commands */
+/*=================*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+/*=======================*/
+/* KGDB support (if any) */
+/*=======================*/
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	1	/* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
diff --git a/include/configs/ml300.h b/include/configs/ml300.h
index 1945918..319923a 100644
--- a/include/configs/ml300.h
+++ b/include/configs/ml300.h
@@ -54,6 +54,7 @@
 
 #define CONFIG_405		1	/* This is a PPC405 CPU		*/
 #define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_XILINX_405	1
 #define CONFIG_XILINX_ML300	1	/* ...on a Xilinx ML300 board	*/
 
 #define CONFIG_SYSTEMACE	1
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index 4974fb4..2a398e8 100644
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -272,10 +272,14 @@
 
 #undef  SPI_INIT			/* no port initialization needed */
 #define SPI_READ        ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
-#define SPI_SDA(bit)    if(bit) immr->im_ioport.iop_pdatd |=  I2C_MOSI; \
-			else    immr->im_ioport.iop_pdatd &= ~I2C_MOSI
-#define SPI_SCL(bit)    if(bit) immr->im_ioport.iop_pdatd |=  I2C_SCLK; \
-			else    immr->im_ioport.iop_pdatd &= ~I2C_SCLK
+#define SPI_SDA(bit)    do {						\
+			if(bit) immr->im_ioport.iop_pdatd |=  I2C_MOSI; \
+			else    immr->im_ioport.iop_pdatd &= ~I2C_MOSI;	\
+			} while (0)
+#define SPI_SCL(bit)    do {						\
+			if(bit) immr->im_ioport.iop_pdatd |=  I2C_SCLK; \
+			else    immr->im_ioport.iop_pdatd &= ~I2C_SCLK;	\
+			} while (0)
 #define SPI_DELAY                       /* No delay is needed */
 #endif /* CONFIG_SOFT_SPI */