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| author | Jagan Teki <jagan@amarulasolutions.com> | 2016-10-25 11:53:23 +0530 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-10-26 18:59:57 +0200 |
| commit | 023ff2f732077a5b3f96e96f191b1045d45d16c4 (patch) | |
| tree | 466986a788b43dbef1586e7af114077e9a1a6058 /include/configs | |
| parent | df10a850c5e3e1bfcd74a01f8478abd4dc88a55b (diff) | |
| download | u-boot-imx-023ff2f732077a5b3f96e96f191b1045d45d16c4.zip u-boot-imx-023ff2f732077a5b3f96e96f191b1045d45d16c4.tar.gz u-boot-imx-023ff2f732077a5b3f96e96f191b1045d45d16c4.tar.bz2 | |
imx6: icorem6: Add NAND support
Add NAND support for Engicam i.CoreM6 qdl board.
Boot Log:
--------
U-Boot SPL 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43)
Trying to boot from NAND
NAND : 512 MiB
U-Boot 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43 +0530)
CPU: Freescale i.MX6SOLO rev1.3 at 792MHz
CPU: Industrial temperature grade (-40C to 105C) at 55C
Reset cause: WDOG
Model: Engicam i.CoreM6 DualLite/Solo Starter Kit
DRAM: 256 MiB
NAND: 512 MiB
MMC: FSL_SDHC: 0
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Hit any key to stop autoboot: 0
icorem6qdl>
Cc: Scott Wood <oss@buserror.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/imx6qdl_icore.h | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h index 6b58447..cd3aa43 100644 --- a/include/configs/imx6qdl_icore.h +++ b/include/configs/imx6qdl_icore.h @@ -27,6 +27,10 @@ /* Environment in MMC */ # if defined(CONFIG_ENV_IS_IN_MMC) # define CONFIG_ENV_OFFSET 0x100000 +/* Environment in NAND */ +# elif defined(CONFIG_ENV_IS_IN_NAND) +# define CONFIG_ENV_OFFSET 0x400000 +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -111,6 +115,20 @@ # define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR #endif +/* NAND */ +#ifdef CONFIG_NAND_MXS +# define CONFIG_SYS_MAX_NAND_DEVICE 1 +# define CONFIG_SYS_NAND_BASE 0x40000000 +# define CONFIG_SYS_NAND_5_ADDR_CYCLE +# define CONFIG_SYS_NAND_ONFI_DETECTION +# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +# define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 + +# define CONFIG_APBH_DMA +# define CONFIG_APBH_DMA_BURST +# define CONFIG_APBH_DMA_BURST8 +#endif + /* Ethernet */ #ifdef CONFIG_FEC_MXC # define IMX_FEC_BASE ENET_BASE_ADDR @@ -125,7 +143,12 @@ /* SPL */ #ifdef CONFIG_SPL -# define CONFIG_SPL_MMC_SUPPORT +# ifdef CONFIG_NAND_MXS +# define CONFIG_SPL_NAND_SUPPORT +# else +# define CONFIG_SPL_MMC_SUPPORT +# endif + # include "imx6_spl.h" # ifdef CONFIG_SPL_BUILD # undef CONFIG_DM_GPIO |