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authorAnton staaf <robotboy@chromium.org>2011-10-03 13:54:58 +0000
committerWolfgang Denk <wd@denx.de>2011-10-25 09:25:02 +0200
commit96d21237ec2b799f60a827ea680594b7ebfdac7f (patch)
tree759465417f77dd359f214a741446745dd2d2d5c1 /include/configs/tegra2-common.h
parent46a6d51c827a12723e7191128fb7aab42c8f5c09 (diff)
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tegra: define CONFIG_SYS_CACHELINE_SIZE for tegra
Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Tom Warren <twarren.nvidia@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Change-Id: I5c4bcfc0bfe59158ff249fe3be6640eec6d3cc76 Acked-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'include/configs/tegra2-common.h')
-rw-r--r--include/configs/tegra2-common.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
index 73e0f05..a9c665c 100644
--- a/include/configs/tegra2-common.h
+++ b/include/configs/tegra2-common.h
@@ -33,6 +33,8 @@
#define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */
#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
#define CONFIG_ENABLE_CORTEXA9 /* enable CPU (A9 complex) */
#include <asm/arch/tegra2.h> /* get chip and board defs */