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| author | Ye.Li <B37916@freescale.com> | 2015-02-02 12:53:23 +0800 |
|---|---|---|
| committer | Peng Fan <Peng.Fan@freescale.com> | 2015-04-29 14:56:33 +0800 |
| commit | 122e17706547c5a72b84332c8f1dc47914ff6279 (patch) | |
| tree | d5e1accafd07a4f23d0a5a703efec2965fcd79bd /include/configs/mx7d_12x12_lpddr3_arm2.h | |
| parent | b81a3cbc857c440098e970c4bff1abd710cfbdd7 (diff) | |
| download | u-boot-imx-122e17706547c5a72b84332c8f1dc47914ff6279.zip u-boot-imx-122e17706547c5a72b84332c8f1dc47914ff6279.tar.gz u-boot-imx-122e17706547c5a72b84332c8f1dc47914ff6279.tar.bz2 | |
MLK-10191-3 imx: mx7: Add support for i.MX7D 12x12 LPDDR3 ARM2 board
Add BSP codes, configuration head file and build target for
12x12 LPDDR3 ARM2 board with basic functions:
ENET, I2C, SD/eMMC/MMC, USB, LCD Splash screen, QSPI, ECSPI,
pfuze3000 PMIC.
Note: pmic and video is still not upstream way
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit ac0d51ef07fdec880e6da318c08d521506640efa)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Conflicts:
boards.cfg
Diffstat (limited to 'include/configs/mx7d_12x12_lpddr3_arm2.h')
| -rw-r--r-- | include/configs/mx7d_12x12_lpddr3_arm2.h | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/include/configs/mx7d_12x12_lpddr3_arm2.h b/include/configs/mx7d_12x12_lpddr3_arm2.h new file mode 100644 index 0000000..8bdc3da --- /dev/null +++ b/include/configs/mx7d_12x12_lpddr3_arm2.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7D 12x12 LPDDR3 ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7D_12X12_LPDDR3_ARM2_CONFIG_H +#define __MX7D_12X12_LPDDR3_ARM2_CONFIG_H + +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +#define PHYS_SDRAM_SIZE SZ_2G + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 1 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#define CONFIG_FEC_DMA_MINALIGN 64 + +/* ENET1 */ +#define IMX_FEC_BASE ENET_IPS_BASE_ADDR + +#ifdef CONFIG_SYS_BOOT_QSPI +#define CONFIG_SYS_USE_QSPI +#define CONFIG_ENV_IS_IN_SPI_FLASH +#elif defined CONFIG_SYS_BOOT_SPINOR +#define CONFIG_SYS_USE_SPINOR +#define CONFIG_ENV_IS_IN_SPI_FLASH +#else +#define CONFIG_SYS_USE_QSPI /* Enable the QSPI flash at default */ +#define CONFIG_ENV_IS_IN_MMC +#endif + +/* PMIC */ +#define CONFIG_PFUZE3000_PMIC_I2C +#ifdef CONFIG_PFUZE3000_PMIC_I2C +#define CONFIG_PMIC_I2C_BUS 0 +#define CONFIG_PMIC_I2C_SLAVE 0x8 +#endif + +#ifdef CONFIG_SYS_USE_SPINOR +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(4, 19)<<8)) +#endif + +#define CONFIG_VIDEO + +#include "mx7d_arm2.h" + +#endif |