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authorHou Zhiqiang <Zhiqiang.Hou@nxp.com>2017-01-10 16:44:15 +0800
committerYork Sun <york.sun@nxp.com>2017-01-18 09:27:59 -0800
commit904110c7ac801b99029b2bca4765c792c9eac582 (patch)
tree5266fd062bff903aff035a6588af17aad261663b /include/configs/ls2080ardb.h
parentee2a51022135a01fa2258b7788702313d0f54dac (diff)
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armv8/fsl-lsch2: refactor the clock system initialization
Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'include/configs/ls2080ardb.h')
-rw-r--r--include/configs/ls2080ardb.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 7f78fd8..5626d88 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -32,7 +32,6 @@
unsigned long get_board_sys_clk(void);
#endif
-#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ 133333333
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)