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authorDirk Eibach <eibach@gdsys.de>2011-01-21 09:31:21 +0100
committerStefan Roese <sr@denx.de>2011-02-07 11:13:16 +0100
commit2da0fc0d0fcdd991220cc120e5bc6d44991a5987 (patch)
treec14838b5dbac4b29f646c72d0b460dd4c11dd83e /include/configs/io.h
parent42d44f631c4e8e5359775bdc098f2fffde4e5c05 (diff)
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ppc4xx: Add DLVision-10G board support
Board support for the Guntermann & Drunck DLVision-10G. Adds support for multiple FPGAs per board for gdsys 405ep architecture. Adds support for dual link osd hardware for gdsys 405ep. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/configs/io.h')
-rw-r--r--include/configs/io.h8
1 files changed, 5 insertions, 3 deletions
diff --git a/include/configs/io.h b/include/configs/io.h
index a66c704..9d2a87d 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -229,13 +229,15 @@
#define CONFIG_SYS_EBC_PB1CR 0x7f318000
/* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_FPGA_BASE 0x7f100000
+#define CONFIG_SYS_FPGA0_BASE 0x7f100000
#define CONFIG_SYS_EBC_PB2AP 0x02025080
/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
#define CONFIG_SYS_EBC_PB2CR 0x7f11a000
-#define CONFIG_SYS_FPGA_RFL_LOW 0x0000
-#define CONFIG_SYS_FPGA_RFL_HIGH 0x3ffe
+#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_FPGA_DONE(k) 0x0010
+
+#define CONFIG_SYS_FPGA_COUNT 1
/* Memory Bank 3 (Latches) initialization */
#define CONFIG_SYS_LATCH_BASE 0x7f200000