summaryrefslogtreecommitdiff
path: root/include/configs/gr_cpci_ax2000.h
diff options
context:
space:
mode:
authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2008-10-16 15:01:15 +0200
committerWolfgang Denk <wd@denx.de>2008-10-18 21:54:03 +0200
commit6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch)
treeae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /include/configs/gr_cpci_ax2000.h
parent71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff)
downloadu-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.zip
u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.gz
u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.bz2
rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'include/configs/gr_cpci_ax2000.h')
-rw-r--r--include/configs/gr_cpci_ax2000.h144
1 files changed, 72 insertions, 72 deletions
diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h
index 5a7a580..bbe635b 100644
--- a/include/configs/gr_cpci_ax2000.h
+++ b/include/configs/gr_cpci_ax2000.h
@@ -61,13 +61,13 @@
#define CONFIG_SYS_CLK_FREQ 20000000 /* 20MHz */
/* Number of SPARC register windows */
-#define CFG_SPARC_NWINDOWS 8
+#define CONFIG_SYS_SPARC_NWINDOWS 8
/*
* Serial console configuration
*/
#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/* Partitions */
#define CONFIG_DOS_PARTITION
@@ -192,28 +192,28 @@
* 0xFF000000 for 16 MB
* 0xFF800000 for 8 MB
*/
-/*#define CFG_NO_FLASH 1*/
-#define CFG_FLASH_BASE 0x00000000
-#define CFG_FLASH_SIZE 0x00800000
+/*#define CONFIG_SYS_NO_FLASH 1*/
+#define CONFIG_SYS_FLASH_BASE 0x00000000
+#define CONFIG_SYS_FLASH_SIZE 0x00800000
#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors */
-#define CFG_MAX_FLASH_SECT 64 /* max num of sects on one chip */
-#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
-#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
/*** CFI CONFIG ***/
-#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
#define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
/* Bypass cache when reading regs from flash memory */
-#define CFG_FLASH_CFI_BYPASS_READ
+#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
/* Buffered writes (32byte/go) instead of single accesses */
-#define CFG_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
/*
* Environment settings
@@ -223,7 +223,7 @@
/* CONFIG_ENV_ADDR need to be at sector boundary */
#define CONFIG_ENV_SIZE 0x8000
#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR (CFG_FLASH_BASE+CFG_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_OVERWRITE 1
/*
@@ -235,59 +235,59 @@
*/
#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM
-#define CFG_SDRAM_BASE 0x40000000
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
#else
-#define CFG_SDRAM_BASE 0x60000000
+#define CONFIG_SYS_SDRAM_BASE 0x60000000
#endif
-#define CFG_SDRAM_SIZE 0x08000000
-#define CFG_SDRAM_END (CFG_SDRAM_BASE+CFG_SDRAM_SIZE)
+#define CONFIG_SYS_SDRAM_SIZE 0x08000000
+#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
/* 4Mb SRAM available */
#if CONFIG_LEON_RAM_SELECT != CONFIG_LEON_RAM_SDRAM_NOSRAM
-#define CFG_SRAM_BASE 0x40000000
-#define CFG_SRAM_SIZE 0x400000
-#define CFG_SRAM_END (CFG_SRAM_BASE+CFG_SRAM_SIZE)
+#define CONFIG_SYS_SRAM_BASE 0x40000000
+#define CONFIG_SYS_SRAM_SIZE 0x400000
+#define CONFIG_SYS_SRAM_END (CONFIG_SYS_SRAM_BASE+CONFIG_SYS_SRAM_SIZE)
#endif
/* Select RAM used to run U-BOOT from... */
#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SRAM
-#define CFG_RAM_BASE CFG_SRAM_BASE
-#define CFG_RAM_SIZE CFG_SRAM_SIZE
-#define CFG_RAM_END CFG_SRAM_END
+#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SRAM_BASE
+#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SRAM_SIZE
+#define CONFIG_SYS_RAM_END CONFIG_SYS_SRAM_END
#else
-#define CFG_RAM_BASE CFG_SDRAM_BASE
-#define CFG_RAM_SIZE CFG_SDRAM_SIZE
-#define CFG_RAM_END CFG_SDRAM_END
+#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
#endif
-#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CFG_PROM_SIZE (8192-CFG_GBL_DATA_SIZE)
-#define CFG_PROM_OFFSET (CFG_GBL_DATA_OFFSET-CFG_PROM_SIZE)
+#define CONFIG_SYS_PROM_SIZE (8192-CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
-#define CFG_INIT_SP_OFFSET (CFG_PROM_OFFSET-32)
-#define CFG_STACK_SIZE (0x10000-32)
+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
+#define CONFIG_SYS_STACK_SIZE (0x10000-32)
-#define CFG_MONITOR_BASE TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-# define CFG_RAMBOOT 1
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT 1
#endif
-#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-#define CFG_MALLOC_END (CFG_INIT_SP_OFFSET-CFG_STACK_SIZE)
-#define CFG_MALLOC_BASE (CFG_MALLOC_END-CFG_MALLOC_LEN)
+#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
+#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
/* relocated monitor area */
-#define CFG_RELOC_MONITOR_MAX_END CFG_MALLOC_BASE
-#define CFG_RELOC_MONITOR_BASE (CFG_RELOC_MONITOR_MAX_END-CFG_MONITOR_LEN)
+#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE
+#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
/* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CFG_RELOC_MONITOR_BASE-TEXT_BASE))
+#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE))
/*
* Ethernet configuration uses on board SMC91C111
@@ -305,23 +305,23 @@
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
-#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
* Various low-level settings
@@ -337,38 +337,38 @@
/***** Gaisler GRLIB IP-Cores Config ********/
/* AMBA Plug & Play info display on startup */
-/*#define CFG_AMBAPP_PRINT_ON_STARTUP*/
+/*#define CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP*/
-#define CFG_GRLIB_SDRAM 0
+#define CONFIG_SYS_GRLIB_SDRAM 0
/* See, GRLIB Docs (grip.pdf) on how to set up
* These the memory controller registers.
*/
-#define CFG_GRLIB_MEMCFG1 (0x10f800ff | (1<<11))
+#define CONFIG_SYS_GRLIB_MEMCFG1 (0x10f800ff | (1<<11))
#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM
-#define CFG_GRLIB_MEMCFG2 0x82206000
+#define CONFIG_SYS_GRLIB_MEMCFG2 0x82206000
#else
-#define CFG_GRLIB_MEMCFG2 0x82205260
+#define CONFIG_SYS_GRLIB_MEMCFG2 0x82205260
#endif
-#define CFG_GRLIB_MEMCFG3 0x0809a000
+#define CONFIG_SYS_GRLIB_MEMCFG3 0x0809a000
-#define CFG_GRLIB_FT_MEMCFG1 (0x10f800ff | (1<<11))
+#define CONFIG_SYS_GRLIB_FT_MEMCFG1 (0x10f800ff | (1<<11))
#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM
-#define CFG_GRLIB_FT_MEMCFG2 0x82206000
+#define CONFIG_SYS_GRLIB_FT_MEMCFG2 0x82206000
#else
-#define CFG_GRLIB_FT_MEMCFG2 0x82205260
+#define CONFIG_SYS_GRLIB_FT_MEMCFG2 0x82205260
#endif
-#define CFG_GRLIB_FT_MEMCFG3 0x0809a000
+#define CONFIG_SYS_GRLIB_FT_MEMCFG3 0x0809a000
/* no DDR controller */
-#define CFG_GRLIB_DDR_CFG 0x00000000
+#define CONFIG_SYS_GRLIB_DDR_CFG 0x00000000
/* no DDR2 Controller */
-#define CFG_GRLIB_DDR2_CFG1 0x00000000
-#define CFG_GRLIB_DDR2_CFG3 0x00000000
+#define CONFIG_SYS_GRLIB_DDR2_CFG1 0x00000000
+#define CONFIG_SYS_GRLIB_DDR2_CFG3 0x00000000
/* Calculate scaler register value from default baudrate */
-#define CFG_GRLIB_APBUART_SCALER \
+#define CONFIG_SYS_GRLIB_APBUART_SCALER \
((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
/* Identification string */