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| author | Tom Warren <twarren@nvidia.com> | 2015-06-22 13:03:44 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-08-05 15:22:51 -0700 |
| commit | 3e8650c0f9cc7fb29bd75c11d0173768fcc80203 (patch) | |
| tree | 240c74dc848121f570ca7b96d49a1159d12ad9ff /include/configs/ea20.h | |
| parent | 66999892b24d3443b24118a6ea400115360e1eb2 (diff) | |
| download | u-boot-imx-3e8650c0f9cc7fb29bd75c11d0173768fcc80203.zip u-boot-imx-3e8650c0f9cc7fb29bd75c11d0173768fcc80203.tar.gz u-boot-imx-3e8650c0f9cc7fb29bd75c11d0173768fcc80203.tar.bz2 | |
Tegra: clocks: Add 38.4MHz OSC support for T210 use
Added 38.4MHz/48MHz entries to pll_x_table for CPU PLL. Needs
to be measured - should be close to 700MHz (1.4G/2).
Note that some freqs aren't in the PLLU table in T210 TRM
(13, 26MHz), so I used the 12MHz table entry for them. They
shouldn't be selected since they're not viable T210 OSC freqs.
Since there are now 2 new OSC defines, all tables (pll_x_table,
PLLU) had to increase by two entries, but since 38.4/48MHz are
not viable osc freqs on T20/30/114, etc, they're just set to 0.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'include/configs/ea20.h')
0 files changed, 0 insertions, 0 deletions