Merge branch 'master' of git://git.denx.de/u-boot-arm

Conflicts:
	arch/arm/include/asm/mach-types.h

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

1 files changed, 31 insertions, 16 deletions

diff --git a/include/configs/eNET.h b/include/configs/eNET.h
index 6a68bf4..361fe61 100644
--- a/include/configs/eNET.h
+++ b/include/configs/eNET.h
@@ -21,6 +21,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm/ibmpc.h>
 /*
  * board/config.h - configuration options, board specific
  */
@@ -52,7 +53,27 @@
  * bottom (processor) board MUST be removed!
  */
 #undef CONFIG_WATCHDOG
-#undef CONFIG_HW_WATCHDOG
+#define CONFIG_HW_WATCHDOG
+
+ /*-----------------------------------------------------------------------
+  * Serial Configuration
+  */
+#define CONFIG_SERIAL_MULTI
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		1843200
+#define CONFIG_BAUDRATE			9600
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1		UART0_BASE
+#define CONFIG_SYS_NS16550_COM2		UART1_BASE
+#define CONFIG_SYS_NS16550_COM3		(0x1000 + UART0_BASE)
+#define CONFIG_SYS_NS16550_COM4		(0x1000 + UART1_BASE)
+#define CONFIG_SYS_NS16550_PORT_MAPPED
 
  /*-----------------------------------------------------------------------
   * Video Configuration
@@ -65,8 +86,6 @@
  */
 #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
 
-#define CONFIG_BAUDRATE		9600
-
 /*-----------------------------------------------------------------------
  * Command line configuration.
  */
@@ -86,9 +105,10 @@
 #define CONFIG_CMD_LOADS	/* loads			*/
 #define CONFIG_CMD_MEMORY	/* md mm nm mw cp cmp crc base loop mtest */
 #define CONFIG_CMD_MISC		/* Misc functions like sleep etc*/
-#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
 #undef CONFIG_CMD_NFS		/* NFS support			*/
 #define CONFIG_CMD_PCI		/* PCI support			*/
+#define CONFIG_CMD_PING		/* ICMP echo support		*/
 #define CONFIG_CMD_RUN		/* run command in env variable	*/
 #define CONFIG_CMD_SAVEENV	/* saveenv			*/
 #define CONFIG_CMD_SETGETDCR	/* DCR support on 4xx		*/
@@ -121,10 +141,7 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ			1024		/* incrementer freq: 1kHz */
-
-						/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define	CONFIG_SYS_HZ			1000		/* incrementer freq: 1kHz */
 
 /*-----------------------------------------------------------------------
  * SDRAM Configuration
@@ -143,7 +160,7 @@
  * CPU Features
  */
 #define CONFIG_SYS_SC520_HIGH_SPEED	0	/* 100 or 133MHz */
-#undef  CONFIG_SYS_SC520_RESET			/* use SC520 MMCR's to reset cpu */
+#define CONFIG_SYS_SC520_RESET			/* use SC520 MMCR's to reset cpu */
 #define CONFIG_SYS_SC520_TIMER			/* use SC520 swtimers */
 #undef  CONFIG_SYS_GENERIC_TIMER		/* use the i8254 PIT timers */
 #undef  CONFIG_SYS_TSC_TIMER			/* use the Pentium TSC timers */
@@ -182,7 +199,7 @@
 					 CONFIG_SYS_FLASH_BASE_1, \
 					 CONFIG_SYS_FLASH_BASE_2}
 #define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
 #define CONFIG_SYS_FLASH_LEGACY_512Kx8
@@ -210,13 +227,11 @@
 #define CONFIG_SYS_THIRD_PCI_IRQ   11
 #define CONFIG_SYS_FORTH_PCI_IRQ   15
 
-/*-----------------------------------------------------------------------
- * Hardware watchdog configuration
+ /*
+ * Network device (TRL8100B) support
  */
-#define CONFIG_SYS_WATCHDOG_PIO_BIT  		0x8000
-#define CONFIG_SYS_WATCHDIG_PIO_DATA 		SC520_PIODATA15_0
-#define CONFIG_SYS_WATCHDIG_PIO_CLR  		SC520_PIOCLR15_0
-#define CONFIG_SYS_WATCHDIG_PIO_SET  		SC520_PIOSET15_0
+#define CONFIG_NET_MULTI
+#define CONFIG_RTL8139
 
 /*-----------------------------------------------------------------------
  * FPGA configuration