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author | TsiChung Liew <Tsi-Chung.Liew@freescale.com> | 2008-08-15 18:24:25 +0000 |
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committer | John Rigby <jrigby@freescale.com> | 2008-08-28 09:16:53 -0600 |
commit | 454e725b3a9537b7f273bbd0cbca180f23a7a6e8 (patch) | |
tree | ebff207846e99262f8d2fa717a2a87a96fd7adcc /include/configs/csb226.h | |
parent | 79e0799cf6e88d98d77b216a55234bf674b59a4e (diff) | |
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ColdFire: Change the SDRAM BRD2WT timing from 3 to 7
The user manuals recommend 7.
Signed-off-by: Kurt Mahan <kmahan@freescale.com>
Acked-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Diffstat (limited to 'include/configs/csb226.h')
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