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authorwdenk <wdenk>2005-04-04 12:08:28 +0000
committerwdenk <wdenk>2005-04-04 12:08:28 +0000
commit101e8dfa2a8b045c6655bf2b3d6fba8d378453cd (patch)
tree1c39acefbaf435ddc2e9f42540eb64ea267cb530 /include/configs/cmc_pu2.h
parent50712ba16e7e469e90952a7f197efa46e2f8e311 (diff)
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Fix timer code for ARM systems: make sure that udelay() does not
reset timers so it's save to use udelay() in timeout code.
Diffstat (limited to 'include/configs/cmc_pu2.h')
-rw-r--r--include/configs/cmc_pu2.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index ef2d1b7..96b7148 100644
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -33,7 +33,7 @@
/* ARM asynchronous clock */
#define AT91C_MAIN_CLOCK 207360000 /* from 18.432 MHz crystal (18432000 / 4 * 45) */
-#define AT91C_MASTER_CLOCK 69120000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
+#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */
#define AT91_SLOW_CLOCK 32768 /* slow clock */
@@ -203,7 +203,7 @@ struct bd_info_ext {
#endif /* __ASSEMBLY__ */
#define CFG_HZ 1000
-#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
+#define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */
/* AT91C_TC_TIMER_DIV1_CLOCK */
#define CONFIG_STACKSIZE (32*1024) /* regular stack */