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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2016-01-27 08:46:11 +0100
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2016-01-31 16:32:56 +0100
commit3709844f2366cd75eacee1deeedadaa507ddc9a1 (patch)
treed89b5d8b6a58a9dc38d18e3415a06a9622932b6e /include/configs/at91-sama5_common.h
parent8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc (diff)
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armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration. In preparation for "arm: cache: Implement cache range check for v7" patch, add these declarations with the appropriate value for the target's SoC or CPU. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'include/configs/at91-sama5_common.h')
-rw-r--r--include/configs/at91-sama5_common.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h
index 9db4a4f..d692106 100644
--- a/include/configs/at91-sama5_common.h
+++ b/include/configs/at91-sama5_common.h
@@ -12,6 +12,8 @@
#include <asm/hardware.h>
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
#define CONFIG_SYS_TEXT_BASE 0x26f00000
/* ARM asynchronous clock */