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authorWolfgang Denk <wd@denx.de>2010-04-01 11:28:32 +0200
committerWolfgang Denk <wd@denx.de>2010-04-01 11:28:32 +0200
commitffa37fc98d71ef930bccd4e9eed37f6ce6b4d6af (patch)
tree206908754219b5cc6e9f03518d34fb95a247bef9 /include/configs/TASREG.h
parentca6e1c136ddb720c3bb2cc043b99f7f06bc46c55 (diff)
parentfd03ea89641d6f6ade6d1a8580c1bb9f52b8542c (diff)
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Merge branch 'next'
Diffstat (limited to 'include/configs/TASREG.h')
-rw-r--r--include/configs/TASREG.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h
index 25f3a26..b69f015 100644
--- a/include/configs/TASREG.h
+++ b/include/configs/TASREG.h
@@ -252,6 +252,17 @@
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
+ CF_CACR_DBWE)
+
/*-----------------------------------------------------------------------
* Memory bank definitions
*/