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authorYork Sun <yorksun@freescale.com>2014-10-27 11:31:32 -0700
committerYork Sun <yorksun@freescale.com>2014-12-05 08:06:08 -0800
commited9e4e427295623197d8dd76a1ca9ac15e085572 (patch)
tree406d2f16e72d4406d8516fcd1bfb4de330bb3bb9 /include/configs/T208xQDS.h
parent2519cb344ee7911ab2f6643449f5dcc32cec9653 (diff)
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mpc85xx/t208xqds: Adjust DDR timing parameters
Adjust timing for dual-rank UDIMM, verified on M3CQ-8GHS3C0E for speed of 1066, 1333, 1600, 1866MT/s. The 1866 timing is copied to 2133 timing in case such DIMM comes available. Also update single-rank 1866 timing. Enable interactive debugging as well. Signed-off-by: York Sun <yorksun@freescale.com> CC: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Diffstat (limited to 'include/configs/T208xQDS.h')
-rw-r--r--include/configs/T208xQDS.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 2f381e7..ebc32f2 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -234,7 +234,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
#define CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR3
-#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51