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| author | Felix Radensky <felix@embedded-sol.com> | 2010-06-28 01:57:39 +0300 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-06-29 21:02:16 +0200 |
| commit | 90b5bf211b85eee10c34cbeb907ce381142b7c99 (patch) | |
| tree | 319f90bd75fcc28742fb6b76b5bb30dfc3316709 /include/configs/P1_P2_RDB.h | |
| parent | d3bee08332fbc9cc5b6dc22ecd34050a85d44d0a (diff) | |
| download | u-boot-imx-90b5bf211b85eee10c34cbeb907ce381142b7c99.zip u-boot-imx-90b5bf211b85eee10c34cbeb907ce381142b7c99.tar.gz u-boot-imx-90b5bf211b85eee10c34cbeb907ce381142b7c99.tar.bz2 | |
tsec: Fix eTSEC2 link problem on P2020RDB
On P2020RDB eTSEC2 is connected to Vitesse VSC8221 PHY via SGMII.
Current TBI PHY settings for SGMII mode cause link problems on
this platform, link never comes up.
Fix this by making TBI PHY settings configurable and add a working
configuration for P2020RDB.
Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'include/configs/P1_P2_RDB.h')
| -rw-r--r-- | include/configs/P1_P2_RDB.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 125911f..b891730 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -425,6 +425,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ETHPRIME "eTSEC1" #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +/* TBI PHY configuration for SGMII mode */ +#define CONFIG_TSEC_TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + #endif /* CONFIG_TSEC_ENET */ /* |