From 90b5bf211b85eee10c34cbeb907ce381142b7c99 Mon Sep 17 00:00:00 2001 From: Felix Radensky Date: Mon, 28 Jun 2010 01:57:39 +0300 Subject: tsec: Fix eTSEC2 link problem on P2020RDB On P2020RDB eTSEC2 is connected to Vitesse VSC8221 PHY via SGMII. Current TBI PHY settings for SGMII mode cause link problems on this platform, link never comes up. Fix this by making TBI PHY settings configurable and add a working configuration for P2020RDB. Signed-off-by: Felix Radensky Acked-by: Andy Fleming --- include/configs/P1_P2_RDB.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include/configs/P1_P2_RDB.h') diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 125911f..b891730 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -425,6 +425,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ETHPRIME "eTSEC1" #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +/* TBI PHY configuration for SGMII mode */ +#define CONFIG_TSEC_TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + #endif /* CONFIG_TSEC_ENET */ /* -- cgit v1.1