summaryrefslogtreecommitdiff
path: root/include/configs/MPC8548CDS.h
diff options
context:
space:
mode:
authorKumar Gala <galak@kernel.crashing.org>2008-12-02 16:08:39 -0600
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2009-01-23 17:03:13 -0600
commit5af0fdd81c3370c3a51421208fda568bdcbbec23 (patch)
tree5fbd9f1b25951176fdaaa9d7eb76dd486930e6e5 /include/configs/MPC8548CDS.h
parenta6e04c344ad1eefd47a75484441b385da815b8df (diff)
downloadu-boot-imx-5af0fdd81c3370c3a51421208fda568bdcbbec23.zip
u-boot-imx-5af0fdd81c3370c3a51421208fda568bdcbbec23.tar.gz
u-boot-imx-5af0fdd81c3370c3a51421208fda568bdcbbec23.tar.bz2
85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards
Introduce a new define to seperate out the virtual address that PCI memory is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'include/configs/MPC8548CDS.h')
-rw-r--r--include/configs/MPC8548CDS.h11
1 files changed, 8 insertions, 3 deletions
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index d76e38c..7110c34 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -365,18 +365,21 @@ extern unsigned long get_clock_freq(void);
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
+#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
+#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#ifdef CONFIG_PCI2
+#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS
+#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
@@ -384,8 +387,9 @@ extern unsigned long get_clock_freq(void);
#endif
#ifdef CONFIG_PCIE1
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
@@ -396,6 +400,7 @@ extern unsigned long get_clock_freq(void);
/*
* RapidIO MMU
*/
+#define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000
#define CONFIG_SYS_RIO_MEM_BUS 0xC0000000
#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
#endif