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authorKumar Gala <galak@kernel.crashing.org>2008-12-02 16:08:37 -0600
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2009-01-23 17:03:13 -0600
commit5f91ef6acdbadec33e0192049e2b24a1d9692f1d (patch)
tree29582e5722c2b16d2ef9506e1155f11e7d3af3f6 /include/configs/MPC8544DS.h
parent10795f42cb94e71bcb262b615084f69dd886399a (diff)
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85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boards
Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead of _IO_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/MPC8544DS.h')
-rw-r--r--include/configs/MPC8544DS.h12
1 files changed, 6 insertions, 6 deletions
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index e31c65b..8d0d784 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -269,7 +269,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
@@ -277,7 +277,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
@@ -285,7 +285,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
@@ -293,7 +293,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BUS
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
-#define CONFIG_SYS_PCIE3_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
@@ -336,8 +336,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
#ifndef CONFIG_PCI_PNP
- #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
- #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BASE
+ #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
+ #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
#endif