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authorJon Loeliger <jdl@freescale.com>2005-07-25 14:05:07 -0500
committerJon Loeliger <jdl@freescale.com>2005-07-25 14:05:07 -0500
commitd9b94f28a442b0013caef99de084d7b72e2d4607 (patch)
tree1b293a551e021a4a696717231ec03206d9f172de /include/configs/MPC8540ADS.h
parent288693abe1f7c23e69479fd85c2c0d8d7fdbf8f2 (diff)
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* Patch by Jon Loeliger, 2005-05-05
Implemented support for MPC8548CDS board. Added DDR II support based on SPD values for MPC85xx boards. This roll-up patch also includes bugfies for the previously published patches: DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
Diffstat (limited to 'include/configs/MPC8540ADS.h')
-rw-r--r--include/configs/MPC8540ADS.h10
1 files changed, 8 insertions, 2 deletions
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 533b587..131c832 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -49,10 +49,12 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
/*
* sysclk for MPC85xx
@@ -342,7 +344,9 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
+#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
+#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
@@ -351,11 +355,13 @@
#if CONFIG_HAS_FEC
#define CONFIG_MPC85XX_FEC 1
+#define CONFIG_MPC85XX_FEC_NAME "FEC"
#define FEC_PHY_ADDR 3
#define FEC_PHYIDX 0
#endif
-#define CONFIG_ETHPRIME "MOTO ENET0"
+/* Options are: TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME "TSEC0"
#endif /* CONFIG_TSEC_ENET */