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authorYork Sun <yorksun@freescale.com>2008-05-15 15:26:27 -0500
committerWolfgang Denk <wd@denx.de>2008-05-19 23:04:24 +0200
commit4ce1e23b5e12283579828b3d23e8fd6e1328a7aa (patch)
tree4b05bf37a8b0993bdc0d4b2b87bd6b652978179e /include/configs/MPC8313ERDB.h
parent180a90abdae72587c0f679edf8991455e559440d (diff)
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Fix 8313ERDB board configuration
Change LCRR clock ratio from 2 to 4 to commodate VSC7385. Correct TSEC1 vs TSEC2 assignment. Define ETHADDR and ETH1ADDR always. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com>
Diffstat (limited to 'include/configs/MPC8313ERDB.h')
-rw-r--r--include/configs/MPC8313ERDB.h14
1 files changed, 6 insertions, 8 deletions
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 6eec240..f9fa535 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -42,9 +42,12 @@
/*
* On-board devices
+ *
+ * TSEC1 is VSC switch
+ * TSEC2 is SoC TSEC
*/
#define CONFIG_VSC7385_ENET
-
+#define CONFIG_TSEC2
#ifdef CFG_66MHZ
#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
@@ -80,7 +83,7 @@
#ifdef CONFIG_VSC7385_ENET
-#define CONFIG_TSEC2
+#define CONFIG_TSEC1
/* The flash address and size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE 0xFE7FE000
@@ -209,7 +212,7 @@
/*
* Local Bus LCRR and LBCR regs
*/
-#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */
+#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_4
#define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \
| (0xFF << LBCR_BMT_SHIFT) \
| 0xF ) /* 0x0004ff0f */
@@ -523,13 +526,8 @@
*/
#define CONFIG_ENV_OVERWRITE
-#ifdef CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:95:01
-#endif
-
-#ifdef CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:95:02
-#endif
#define CONFIG_IPADDR 10.0.0.2
#define CONFIG_SERVERIP 10.0.0.1