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| author | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2007-09-23 01:29:43 +0900 |
|---|---|---|
| committer | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2007-09-23 01:29:43 +0900 |
| commit | b8685affe614ccf5f4ec66252b30e2e524d18948 (patch) | |
| tree | 05bc55b8a4a0451e6500f1f52651d81c0f48f012 /include/configs/CPCI405DT.h | |
| parent | 69df3c4da0c93017cceb25a366e794570bd0ed98 (diff) | |
| parent | 66dcad3a9a53e0766d90e0084123bd8529522fb0 (diff) | |
| download | u-boot-imx-b8685affe614ccf5f4ec66252b30e2e524d18948.zip u-boot-imx-b8685affe614ccf5f4ec66252b30e2e524d18948.tar.gz u-boot-imx-b8685affe614ccf5f4ec66252b30e2e524d18948.tar.bz2 | |
Merge git://www.denx.de/git/u-boot
Conflicts:
CREDITS
Diffstat (limited to 'include/configs/CPCI405DT.h')
| -rw-r--r-- | include/configs/CPCI405DT.h | 63 |
1 files changed, 37 insertions, 26 deletions
diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 2260327..29f9292 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -56,28 +56,44 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ + +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_SEND_HOSTNAME ) - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM ) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_BSP +#define CONFIG_CMD_EEPROM + #if 0 /* test-only */ #define CONFIG_NETCONSOLE @@ -95,11 +111,6 @@ #undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CFG_NAND_LEGACY - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -115,7 +126,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -314,7 +325,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif |