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authorYork Sun <yorksun@freescale.com>2013-06-25 11:37:48 -0700
committerYork Sun <yorksun@freescale.com>2013-08-09 12:41:39 -0700
commitc63e137014cf148bc1d234128941dccee3d519ae (patch)
treeafb69c22c33459d14a174973083e2a70e5f49ea7 /include/bedbug
parentb61e06156660579ea6e248abd2506ebdd85e7a14 (diff)
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powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: York Sun <yorksun@freescale.com>
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