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author | Eugene O'Brien <eugene.obrien@advantechamt.com> | 2007-10-18 17:29:04 +0200 |
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committer | Stefan Roese <sr@denx.de> | 2007-10-31 21:20:50 +0100 |
commit | f6ba9b56607d4b27550301c7c7f6b55b654fd62a (patch) | |
tree | 345e74b8e67c08c7420eecbcd899ac1689410dd0 /include/asm-ppc | |
parent | c36c68160333ac5fe41ec3db12a728b7075b3912 (diff) | |
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ppc4xx: Define CONFIG_BOOKE for all PPC440 based processors
CONFIG_BOOKE must be defined for PPC440 processors so that the proper SPR
number is used to access system registers.
Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/asm-ppc')
-rw-r--r-- | include/asm-ppc/processor.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 451ee94..f58b38a 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -91,6 +91,11 @@ /* Special Purpose Registers (SPRNs)*/ +/* PPC440 Architecture is BOOK-E */ +#ifdef CONFIG_440 +#define CONFIG_BOOKE +#endif + #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ #define SPRN_CTR 0x009 /* Count Register */ #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ |