Merge branch 'master' of /home/stefan/git/u-boot/u-boot into for-1.3.2-ver2

5 files changed, 105 insertions, 46 deletions

diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 496fc72..d769d70 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -720,11 +720,10 @@ typedef struct ccsr_tsec {
 } ccsr_tsec_t;
 
 /*
- * PIC Registers(0x2_6000-0x4_0000-0x8_0000)
+ * PIC Registers(0x4_0000-0x8_0000)
  */
 typedef struct ccsr_pic {
-	char 	res0[106496];	/* 0x26000-0x40000 */
-	char	res1[64];
+	char	res1[64];	/* 0x40000 */
 	uint	ipidr0;		/* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
 	char	res2[12];
 	uint	ipidr1;		/* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
@@ -1619,25 +1618,25 @@ typedef struct ccsr_gur {
 
 #define PORDEVSR_PCI	(0x00800000)	/* PCI Mode */
 
-typedef struct immap {
-	ccsr_local_ecm_t	im_local_ecm;
-	ccsr_ddr_t		im_ddr;
-	ccsr_i2c_t		im_i2c;
-	ccsr_duart_t		im_duart;
-	ccsr_lbc_t		im_lbc;
-	ccsr_pcix_t		im_pcix;
-	ccsr_pcix_t		im_pcix2;
-	char			reserved[90112];
-	ccsr_l2cache_t		im_l2cache;
-	ccsr_dma_t		im_dma;
-	ccsr_tsec_t		im_tsec1;
-	ccsr_tsec_t		im_tsec2;
-	ccsr_pic_t		im_pic;
-	ccsr_cpm_t		im_cpm;
-	ccsr_rio_t		im_rio;
-	ccsr_gur_t		im_gur;
-} immap_t;
-
-extern immap_t  *immr;
+#define CFG_MPC85xx_GUTS_OFFSET	(0xE0000)
+#define CFG_MPC85xx_GUTS_ADDR	(CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET)
+#define CFG_MPC85xx_ECM_OFFSET	(0x0000)
+#define CFG_MPC85xx_ECM_ADDR	(CFG_IMMR + CFG_MPC85xx_ECM_OFFSET)
+#define CFG_MPC85xx_DDR_OFFSET	(0x2000)
+#define CFG_MPC85xx_DDR_ADDR	(CFG_IMMR + CFG_MPC85xx_DDR_OFFSET)
+#define CFG_MPC85xx_LBC_OFFSET	(0x5000)
+#define CFG_MPC85xx_LBC_ADDR	(CFG_IMMR + CFG_MPC85xx_LBC_OFFSET)
+#define CFG_MPC85xx_PCIX_OFFSET	(0x8000)
+#define CFG_MPC85xx_PCIX_ADDR	(CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET)
+#define CFG_MPC85xx_PCIX2_OFFSET	(0x9000)
+#define CFG_MPC85xx_PCIX2_ADDR	(CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET)
+#define CFG_MPC85xx_L2_OFFSET	(0x20000)
+#define CFG_MPC85xx_L2_ADDR	(CFG_IMMR + CFG_MPC85xx_L2_OFFSET)
+#define CFG_MPC85xx_DMA_OFFSET	(0x21000)
+#define CFG_MPC85xx_DMA_ADDR	(CFG_IMMR + CFG_MPC85xx_DMA_OFFSET)
+#define CFG_MPC85xx_PIC_OFFSET	(0x40000)
+#define CFG_MPC85xx_PIC_ADDR	(CFG_IMMR + CFG_MPC85xx_PIC_OFFSET)
+#define CFG_MPC85xx_CPM_OFFSET	(0x80000)
+#define CFG_MPC85xx_CPM_ADDR	(CFG_IMMR + CFG_MPC85xx_CPM_OFFSET)
 
 #endif /*__IMMAP_85xx__*/
diff --git a/include/asm-ppc/immap_fsl_pci.h b/include/asm-ppc/immap_fsl_pci.h
index bd732b6..6715064 100644
--- a/include/asm-ppc/immap_fsl_pci.h
+++ b/include/asm-ppc/immap_fsl_pci.h
@@ -144,7 +144,9 @@ typedef struct ccsr_pci {
 	u32	perr_cap1;	/* 0xe2c - PCIE Error Capture Register 1 */
 	u32	perr_cap2;	/* 0xe30 - PCIE Error Capture Register 2 */
 	u32	perr_cap3;	/* 0xe34 - PCIE Error Capture Register 3 */
-	char	res23[456];	/*     (- #x1000 #xe38) 456 */
+	char	res23[200];
+	u32	pdb_stat;	/* 0xf00 - PCIE Debug Status */
+	char	res24[252];
 } ccsr_fsl_pci_t;
 
 #endif /*__IMMAP_fsl_pci__*/
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index 11dfa1c..91c9c1e 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -121,13 +121,43 @@ static inline void isync(void)
 #define iobarrier_w()  eieio()
 
 /*
+ * Non ordered and non-swapping "raw" accessors
+ */
+#define __iomem
+#define PCI_FIX_ADDR(addr)	(addr)
+
+static inline unsigned char __raw_readb(const volatile void __iomem *addr)
+{
+	return *(volatile unsigned char *)PCI_FIX_ADDR(addr);
+}
+static inline unsigned short __raw_readw(const volatile void __iomem *addr)
+{
+	return *(volatile unsigned short *)PCI_FIX_ADDR(addr);
+}
+static inline unsigned int __raw_readl(const volatile void __iomem *addr)
+{
+	return *(volatile unsigned int *)PCI_FIX_ADDR(addr);
+}
+static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
+{
+	*(volatile unsigned char *)PCI_FIX_ADDR(addr) = v;
+}
+static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
+{
+	*(volatile unsigned short *)PCI_FIX_ADDR(addr) = v;
+}
+static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
+{
+	*(volatile unsigned int *)PCI_FIX_ADDR(addr) = v;
+}
+
+/*
  * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
  *
  * Read operations have additional twi & isync to make sure the read
  * is actually performed (i.e. the data has come back) before we start
  * executing any following instructions.
  */
-#define __iomem
 extern inline int in_8(const volatile unsigned char __iomem *addr)
 {
 	int ret;
@@ -208,4 +238,30 @@ extern inline void out_be32(volatile unsigned __iomem *addr, int val)
 	__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
 }
 
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+typedef unsigned long phys_addr_t;
+
+#define MAP_NOCACHE	(0)
+#define MAP_WRCOMBINE	(0)
+#define MAP_WRBACK	(0)
+#define MAP_WRTHROUGH	(0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+	return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
 #endif
diff --git a/include/asm-ppc/iopin_85xx.h b/include/asm-ppc/iopin_85xx.h
index f854df6..daddb55 100644
--- a/include/asm-ppc/iopin_85xx.h
+++ b/include/asm-ppc/iopin_85xx.h
@@ -23,121 +23,121 @@ typedef struct {
 
 extern __inline__ void iopin_set_high (iopin_t * iopin)
 {
-	volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+	volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
 	datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
 extern __inline__ void iopin_set_low (iopin_t * iopin)
 {
-	volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+	volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
 	datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
 extern __inline__ uint iopin_is_high (iopin_t * iopin)
 {
-	volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+	volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
 	return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
 extern __inline__ uint iopin_is_low (iopin_t * iopin)
 {
-	volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+	volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
 	return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
 }
 
 extern __inline__ void iopin_set_out (iopin_t * iopin)
 {
-	volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+	volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
 	dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
 extern __inline__ void iopin_set_in (iopin_t * iopin)
 {
-	volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+	volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
 	dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
 extern __inline__ uint iopin_is_out (iopin_t * iopin)
 {
-	volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+	volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
 	return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
 extern __inline__ uint iopin_is_in (iopin_t * iopin)
 {
-	volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+	volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
 	return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
 }
 
 extern __inline__ void iopin_set_odr (iopin_t * iopin)
 {
-	volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+	volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
 	odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
 extern __inline__ void iopin_set_act (iopin_t * iopin)
 {
-	volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+	volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
 	odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
 extern __inline__ uint iopin_is_odr (iopin_t * iopin)
 {
-	volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+	volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
 	return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
 extern __inline__ uint iopin_is_act (iopin_t * iopin)
 {
-	volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+	volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
 	return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
 }
 
 extern __inline__ void iopin_set_ded (iopin_t * iopin)
 {
-	volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+	volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
 	parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
 extern __inline__ void iopin_set_gen (iopin_t * iopin)
 {
-	volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+	volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
 	parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
 extern __inline__ uint iopin_is_ded (iopin_t * iopin)
 {
-	volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+	volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
 	return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
 extern __inline__ uint iopin_is_gen (iopin_t * iopin)
 {
-	volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+	volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
 	return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
 }
 
 extern __inline__ void iopin_set_opt2 (iopin_t * iopin)
 {
-	volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+	volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
 	sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
 extern __inline__ void iopin_set_opt1 (iopin_t * iopin)
 {
-	volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+	volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
 	sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
 extern __inline__ uint iopin_is_opt2 (iopin_t * iopin)
 {
-	volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+	volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
 	return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
 extern __inline__ uint iopin_is_opt1 (iopin_t * iopin)
 {
-	volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+	volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
 	return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
 }
 
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index edcb3b9..b19abe7 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -413,7 +413,9 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
 #define LAWAR_TRGT_IF_PCI1	0x00000000
 #define LAWAR_TRGT_IF_PCIX	0x00000000
 #define LAWAR_TRGT_IF_PCI2	0x00100000
-#define LAWAR_TRGT_IF_PEX	0x00200000
+#define LAWAR_TRGT_IF_PCIE1	0x00200000
+#define LAWAR_TRGT_IF_PCIE2	0x00100000
+#define LAWAR_TRGT_IF_PCIE3	0x00300000
 #define LAWAR_TRGT_IF_LBC	0x00400000
 #define LAWAR_TRGT_IF_CCSR	0x00800000
 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000