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| author | Anton Vorontsov <avorontsov@ru.mvista.com> | 2008-05-29 18:14:56 +0400 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2008-06-10 12:30:13 -0500 |
| commit | f9023afbdfd9f27e7c38f3cce965746e56d62dd3 (patch) | |
| tree | 6d936680639f5bf2f50426ed03e430d886e94442 /include/asm-ppc/fsl_lbc.h | |
| parent | bf30bb1f7c954d7855d9b23624b33b00c50b4697 (diff) | |
| download | u-boot-imx-f9023afbdfd9f27e7c38f3cce965746e56d62dd3.zip u-boot-imx-f9023afbdfd9f27e7c38f3cce965746e56d62dd3.tar.gz u-boot-imx-f9023afbdfd9f27e7c38f3cce965746e56d62dd3.tar.bz2 | |
83xx/85xx: further localbus cleanups
move the BRx_* and ORx_* left behind in mpc85xx.h
The same is needed for mpc8xx.h and mpc8260.h (defines are almost
the same, just few differences which needs some attention though).
But the bad news for mpc8xx and mpc8260 is that there are a lot of users
of these defines. So this cleanup I'll leave for the "better times".
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'include/asm-ppc/fsl_lbc.h')
| -rw-r--r-- | include/asm-ppc/fsl_lbc.h | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index a129dca..4529f02 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -44,7 +44,11 @@ #define BR_MSEL_SHIFT 5 #define BR_MS_GPCM 0x00000000 /* GPCM */ #define BR_MS_FCM 0x00000020 /* FCM */ +#ifdef CONFIG_MPC83xx #define BR_MS_SDRAM 0x00000060 /* SDRAM */ +#elif defined(CONFIG_MPC85xx) +#define BR_MS_SDRAM 0x00000000 /* SDRAM */ +#endif #define BR_MS_UPMA 0x00000080 /* UPMA */ #define BR_MS_UPMB 0x000000A0 /* UPMB */ #define BR_MS_UPMC 0x000000C0 /* UPMC */ @@ -80,8 +84,8 @@ #define OR_GPCM_CSNT_SHIFT 11 #define OR_GPCM_ACS 0x00000600 #define OR_GPCM_ACS_SHIFT 9 -#define OR_GPCM_ACS_0b10 0x00000400 -#define OR_GPCM_ACS_0b11 0x00000600 +#define OR_GPCM_ACS_DIV2 0x00000600 +#define OR_GPCM_ACS_DIV4 0x00000400 #define OR_GPCM_XACS 0x00000100 #define OR_GPCM_XACS_SHIFT 8 #define OR_GPCM_SCY 0x000000F0 @@ -110,6 +114,10 @@ #define OR_GPCM_EAD 0x00000001 #define OR_GPCM_EAD_SHIFT 0 +/* helpers to convert values into an OR address mask (GPCM mode) */ +#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ +#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20) + #define OR_FCM_AM 0xFFFF8000 #define OR_FCM_AM_SHIFT 15 #define OR_FCM_BCTLD 0x00001000 @@ -153,6 +161,11 @@ #define OR_UPM_EAD 0x00000001 #define OR_UPM_EAD_SHIFT 0 +#define MxMR_OP_NORM 0x00000000 /* Normal Operation */ +#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */ +#define MxMR_OP_WARR 0x10000000 /* Write to Array */ +#define MxMR_BSEL 0x80000000 /* Bus Select */ + #define OR_SDRAM_AM 0xFFFF8000 #define OR_SDRAM_AM_SHIFT 15 #define OR_SDRAM_XAM 0x00006000 |