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| author | Kumar Gala <galak@kernel.crashing.org> | 2009-09-15 22:21:58 -0500 |
|---|---|---|
| committer | Tom Rix <Tom.Rix@windriver.com> | 2009-10-03 09:04:33 -0500 |
| commit | 68f9c1e754bd3c68495d0952c29853035c59e60a (patch) | |
| tree | 5127b23bc93990603b0c2c28bea45c24ee054e2c /include/asm-ppc/cache.h | |
| parent | d4b5d60d2ae39c1d74b78e8b8f4f1ddd29c7953b (diff) | |
| download | u-boot-imx-68f9c1e754bd3c68495d0952c29853035c59e60a.zip u-boot-imx-68f9c1e754bd3c68495d0952c29853035c59e60a.tar.gz u-boot-imx-68f9c1e754bd3c68495d0952c29853035c59e60a.tar.bz2 | |
ppc/85xx: Fix LCRR_CLKDIV defines
For some reason the CLKDIV field varies between SoC in how it interprets
the bit values.
All 83xx and early (e500v1) PQ3 devices support:
clk/2: CLKDIV = 2
clk/4: CLKDIV = 4
clk/8: CLKDIV = 8
Newer PQ3 (e500v2) and MPC86xx support:
clk/4: CLKDIV = 2
clk/8: CLKDIV = 4
clk/16: CLKDIV = 8
Ensure that the MPC86xx and MPC85xx still get the same behavior and make
the defines reflect their logical view (not the value of the field).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
Diffstat (limited to 'include/asm-ppc/cache.h')
0 files changed, 0 insertions, 0 deletions