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| author | Tom Rix <Tom.Rix@windriver.com> | 2010-01-18 08:08:32 -0600 |
|---|---|---|
| committer | Tom Rix <Tom.Rix@windriver.com> | 2010-01-18 08:08:32 -0600 |
| commit | a7709d926dbc7cb1541034fcf2b21ce3e838cb12 (patch) | |
| tree | 72c58261577bc00d98dbd208e4fa95dfbb2487a5 /include/asm-blackfin/mach-bf548/BF542_def.h | |
| parent | 1c2a8e359ebbec0dbef62f5b54c72f9cd72ccd59 (diff) | |
| parent | 88ffb2665cd066b6b20cfaade13929d4e8428dde (diff) | |
| download | u-boot-imx-a7709d926dbc7cb1541034fcf2b21ce3e838cb12.zip u-boot-imx-a7709d926dbc7cb1541034fcf2b21ce3e838cb12.tar.gz u-boot-imx-a7709d926dbc7cb1541034fcf2b21ce3e838cb12.tar.bz2 | |
Merge branch 't-ml-master' into t-master
Diffstat (limited to 'include/asm-blackfin/mach-bf548/BF542_def.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf548/BF542_def.h | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/include/asm-blackfin/mach-bf548/BF542_def.h b/include/asm-blackfin/mach-bf548/BF542_def.h index 40fe555..1324a13 100644 --- a/include/asm-blackfin/mach-bf548/BF542_def.h +++ b/include/asm-blackfin/mach-bf548/BF542_def.h @@ -113,20 +113,5 @@ #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF542_proc__ */ |