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| author | Michal Simek <monstr@monstr.eu> | 2007-05-08 00:32:35 +0200 |
|---|---|---|
| committer | Michal Simek <monstr@monstr.eu> | 2007-05-08 00:32:35 +0200 |
| commit | 3c4bd60de15d79ddfc0cf3170a55847b2025d93f (patch) | |
| tree | 891b84b58f13a5f45536a243585b9d94c253a410 /include/asm-blackfin/cplb.h | |
| parent | fb05f6da35ea1c15c553abe6f23f656bf18dc5db (diff) | |
| parent | ac4cd59d59c9bf3f89cb7a344abf8184d678f562 (diff) | |
| download | u-boot-imx-3c4bd60de15d79ddfc0cf3170a55847b2025d93f.zip u-boot-imx-3c4bd60de15d79ddfc0cf3170a55847b2025d93f.tar.gz u-boot-imx-3c4bd60de15d79ddfc0cf3170a55847b2025d93f.tar.bz2 | |
Merge git://www.denx.de/git/u-boot
Conflicts:
include/asm-microblaze/microblaze_intc.h
include/linux/stat.h
Diffstat (limited to 'include/asm-blackfin/cplb.h')
| -rw-r--r-- | include/asm-blackfin/cplb.h | 38 |
1 files changed, 35 insertions, 3 deletions
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h index 7715f64..9d8d9ec 100644 --- a/include/asm-blackfin/cplb.h +++ b/include/asm-blackfin/cplb.h @@ -7,14 +7,15 @@ ************************************************************************/ /* Defines necessary for cplb initialisation routines. */ - #ifndef _CPLB_H #define _CPLB_H +#define CONFIG_BLKFIN_WT + #define CPLB_ENABLE_ICACHE_P 0 #define CPLB_ENABLE_DCACHE_P 1 #define CPLB_ENABLE_DCACHE2_P 2 -#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated!*/ +#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */ #define CPLB_ENABLE_ICPLBS_P 4 #define CPLB_ENABLE_DCPLBS_P 5 @@ -45,4 +46,35 @@ #define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL -#endif /* _CPLB_H */ +/* Data Attibutes*/ + +#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) +#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) + +/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ + +#define ANOMALY_05000158 0x200 + +#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) +#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) + +#else /*Write Through */ +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) +#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) +#endif + +#if defined(CONFIG_BF561) +#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 4) /* SDRAM +L1 + ASYNC_Memory */ +#else +#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM + L1 + ASYNC_Memory */ +#endif +#endif /* _CPLB_H */ |