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authorPrafulla Wadaskar <prafulla@marvell.com>2009-08-20 20:59:28 +0530
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2009-09-01 22:34:03 +0200
commit49d2cb4d6153a6c18249dccb5de5cffeb261a61c (patch)
treee130eb93319d2801f3afd37483b54a9f58355397 /include/asm-arm/arch-kirkwood/cpu.h
parent9453967e28c5e3abbf856f95735ea69bae1e77fa (diff)
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arm: Kirkwood: add SYSRSTn Duration Counter Support
This feature can be used to trigger special command "sysrstcmd" using reset key long press event and environment variable "sysrstdelay" is set (useful for reset to factory or manufacturing mode execution) Kirkwood SoC implements a hardware-based SYSRSTn duration counter. When SYSRSTn is asserted low, a SYSRSTn duration counter is running. The counter value is stored in the SYSRSTn Length Counter Register The counter is based on the 25-MHz reference clock (40ns) It is a 29-bit counter, yielding a maximum counting duration of 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value, it remains at this value until counter reset is triggered by setting bit 31 of KW_REG_SYSRST_CNT Implementation: Upon long reset assertion (> ${sysrstdelay} in secs) sysrstcmd will be executed if pre-defined in environment variables. This feature will be disabled if "sysrstdelay" variable is unset. for-ex. setenv sysrst_cmd "echo starting factory reset; nand erase 0xa0000 0x20000; echo finish ed sysrst command;" will erase particular nand sector if triggered by this event Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Diffstat (limited to 'include/asm-arm/arch-kirkwood/cpu.h')
-rw-r--r--include/asm-arm/arch-kirkwood/cpu.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-arm/arch-kirkwood/cpu.h b/include/asm-arm/arch-kirkwood/cpu.h
index d1440af..b3022a3 100644
--- a/include/asm-arm/arch-kirkwood/cpu.h
+++ b/include/asm-arm/arch-kirkwood/cpu.h
@@ -36,6 +36,8 @@
((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c)
#define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34)
+#define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50)
+#define SYSRST_CNT_1SEC_VAL (25*1000000)
#define KW_REG_MPP_OUT_DRV_REG (KW_MPP_BASE + 0xE0)
enum memory_bank {