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author | Peng Fan <Peng.Fan@freescale.com> | 2015-11-04 16:30:47 +0800 |
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committer | Peng Fan <Peng.Fan@freescale.com> | 2015-11-09 14:57:19 +0800 |
commit | 6cf684ae53011effa838ce2277fabfec4ae42ea0 (patch) | |
tree | 6e3496671cae1b8db6c83b42cb9d4fb0e09b5a66 /fs/ubifs/crc16.h | |
parent | 8baeadb8fc732b69a49d30e629f9aa95f460bd5c (diff) | |
download | u-boot-imx-l5.1.1_2.1.0-ga.zip u-boot-imx-l5.1.1_2.1.0-ga.tar.gz u-boot-imx-l5.1.1_2.1.0-ga.tar.bz2 |
MLK-11825 imx: mx6dqp: update ddr script to 1.13rel_imx_3.14.52_1.1.1_garel_imx_3.14.52_1.1.0_gal5.1.1_2.1.0-gaimx_v2015.04_3.14.52_1.1.0_ga
http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/8111e4d0cd81226899be637013048281e3c097b4
http://compass.freescale.net/livelink/livelink?func=ll&objId=234753630&objAction=browse&viewType=1
arik_r2_sabre_ddr3_528_1.13.inc is for sabre-AI
arik_r2_sdb_ddr3_528_1.13.inc is for sabresd
1.13<-1.12:
Change log:
1. Remove 20c4080
1.12<-1.10
Change log:
1. NoC register DDRCONF change to 0 which is compatible
for only CS0 is used on board
2. Change 2 values to compatible with our DDR aid script,
these two registers doesn’t have any effect on current system
tRPA = 0;
//this bit only used in DDR2 mode
tAOFPD/tAONPD=0x4;
//These register only works when MDPDC. SLOW_PD = 1 which is 0 in script
Test results:
One mx6qp-sdb and one mx6qp-ard board and one mx6qp-ard board passed
60 hours memtester stress teset.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit 5fb08a4dcc7b8478fc4236b90ad8dc2190cf94e7)
Diffstat (limited to 'fs/ubifs/crc16.h')
0 files changed, 0 insertions, 0 deletions