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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-05-09 10:47:05 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-05-09 11:50:14 +0200
commitd2a3e911390f9fc4d8c0ee4b3c7fc75f4fd3fd19 (patch)
treed71aae6d706d1f3b01da5f944e247abe308feea0 /drivers
parent7904b70885f3c589c239f6ac978f299a6744557f (diff)
parent173d294b94cfec10063a5be40934d6d8fb7981ce (diff)
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Merge branch 'u-boot/master'
Conflicts: drivers/net/Makefile (trivial merge)
Diffstat (limited to 'drivers')
-rw-r--r--drivers/ddr/fsl/Makefile19
-rw-r--r--drivers/ddr/fsl/ctrl_regs.c743
-rw-r--r--drivers/ddr/fsl/ddr4_dimm_params.c300
-rw-r--r--drivers/ddr/fsl/fsl_ddr_gen4.c234
-rw-r--r--drivers/ddr/fsl/interactive.c391
-rw-r--r--drivers/ddr/fsl/lc_common_dimm_params.c407
-rw-r--r--drivers/ddr/fsl/main.c31
-rw-r--r--drivers/ddr/fsl/mpc85xx_ddr_gen3.c52
-rw-r--r--drivers/ddr/fsl/options.c142
-rw-r--r--drivers/ddr/fsl/util.c26
-rw-r--r--drivers/dfu/dfu.c2
-rw-r--r--drivers/dfu/dfu_mmc.c109
-rw-r--r--drivers/i2c/fsl_i2c.c41
-rw-r--r--drivers/i2c/mxc_i2c.c18
-rw-r--r--drivers/misc/fsl_ifc.c7
-rw-r--r--drivers/mmc/fsl_esdhc_spl.c32
-rw-r--r--drivers/mtd/nand/diskonchip.c1780
-rw-r--r--drivers/mtd/nand/fsl_ifc_spl.c13
-rw-r--r--drivers/mtd/spi/fsl_espi_spl.c29
-rw-r--r--drivers/net/e1000.c1
-rw-r--r--drivers/net/fm/fm.c12
-rw-r--r--drivers/net/fm/memac_phy.c12
-rw-r--r--drivers/net/inca-ip_sw.c793
-rw-r--r--drivers/net/lan91c96.h6
-rw-r--r--drivers/net/pcnet.c122
-rw-r--r--drivers/net/phy/atheros.c2
-rw-r--r--drivers/net/phy/vitesse.c2
-rw-r--r--drivers/net/zynq_gem.c4
-rw-r--r--drivers/pcmcia/mpc8xx_pcmcia.c2
-rw-r--r--drivers/pcmcia/rpx_pcmcia.c4
-rw-r--r--drivers/qe/qe.c2
-rw-r--r--drivers/qe/qe.h2
-rw-r--r--drivers/serial/serial.c4
-rw-r--r--drivers/serial/serial_zynq.c18
-rw-r--r--drivers/usb/gadget/Makefile1
-rw-r--r--drivers/usb/gadget/ci_udc.c31
-rw-r--r--drivers/usb/gadget/ci_udc.h65
-rw-r--r--drivers/usb/gadget/f_dfu.c3
-rw-r--r--drivers/usb/gadget/f_mass_storage.c11
-rw-r--r--drivers/usb/gadget/f_thor.c15
-rw-r--r--drivers/usb/gadget/g_dnl.c66
-rw-r--r--drivers/usb/gadget/storage_common.c4
-rw-r--r--drivers/usb/gadget/usbstring.c3
-rw-r--r--drivers/usb/host/Makefile1
-rw-r--r--drivers/usb/host/ehci-exynos.c3
-rw-r--r--drivers/usb/host/ehci-fsl.c38
-rw-r--r--drivers/usb/host/ehci-hcd.c56
-rw-r--r--drivers/usb/host/ehci-rmobile.c130
-rw-r--r--drivers/usb/host/xhci-exynos5.c3
-rw-r--r--drivers/usb/musb-new/musb_uboot.c5
50 files changed, 2638 insertions, 3159 deletions
diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
index 265204f..df66c07 100644
--- a/drivers/ddr/fsl/Makefile
+++ b/drivers/ddr/fsl/Makefile
@@ -1,19 +1,20 @@
#
-# Copyright 2008-2011 Freescale Semiconductor, Inc.
+# Copyright 2008-2014 Freescale Semiconductor, Inc.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License
# Version 2 as published by the Free Software Foundation.
#
-obj-$(CONFIG_SYS_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
- lc_common_dimm_params.o
+obj-$(CONFIG_SYS_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
+ lc_common_dimm_params.o
+obj-$(CONFIG_SYS_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \
+ lc_common_dimm_params.o
+obj-$(CONFIG_SYS_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \
+ lc_common_dimm_params.o
+obj-$(CONFIG_SYS_FSL_DDR4) += main.o util.o ctrl_regs.o options.o \
+ lc_common_dimm_params.o
-obj-$(CONFIG_SYS_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \
- lc_common_dimm_params.o
-
-obj-$(CONFIG_SYS_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \
- lc_common_dimm_params.o
ifdef CONFIG_DDR_SPD
SPD := y
endif
@@ -24,6 +25,7 @@ ifdef SPD
obj-$(CONFIG_SYS_FSL_DDR1) += ddr1_dimm_params.o
obj-$(CONFIG_SYS_FSL_DDR2) += ddr2_dimm_params.o
obj-$(CONFIG_SYS_FSL_DDR3) += ddr3_dimm_params.o
+obj-$(CONFIG_SYS_FSL_DDR4) += ddr4_dimm_params.o
endif
obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
@@ -32,3 +34,4 @@ obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o
obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o
obj-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o
obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o
+obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 0882932..78e82bb 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -17,20 +17,6 @@
#include <fsl_immap.h>
#include <asm/io.h>
-#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
-
-static u32 fsl_ddr_get_version(void)
-{
- struct ccsr_ddr __iomem *ddr;
- u32 ver_major_minor_errata;
-
- ddr = (void *)_DDR_ADDR;
- ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8;
- ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8;
-
- return ver_major_minor_errata;
-}
-
unsigned int picos_to_mclk(unsigned int picos);
/*
@@ -81,6 +67,39 @@ static inline int fsl_ddr_get_rtt(void)
return rtt;
}
+#ifdef CONFIG_SYS_FSL_DDR4
+/*
+ * compute CAS write latency according to DDR4 spec
+ * CWL = 9 for <= 1600MT/s
+ * 10 for <= 1866MT/s
+ * 11 for <= 2133MT/s
+ * 12 for <= 2400MT/s
+ * 14 for <= 2667MT/s
+ * 16 for <= 2933MT/s
+ * 18 for higher
+ */
+static inline unsigned int compute_cas_write_latency(void)
+{
+ unsigned int cwl;
+ const unsigned int mclk_ps = get_memory_clk_period_ps();
+ if (mclk_ps >= 1250)
+ cwl = 9;
+ else if (mclk_ps >= 1070)
+ cwl = 10;
+ else if (mclk_ps >= 935)
+ cwl = 11;
+ else if (mclk_ps >= 833)
+ cwl = 12;
+ else if (mclk_ps >= 750)
+ cwl = 14;
+ else if (mclk_ps >= 681)
+ cwl = 16;
+ else
+ cwl = 18;
+
+ return cwl;
+}
+#else
/*
* compute the CAS write latency according to DDR3 spec
* CWL = 5 if tCK >= 2.5ns
@@ -119,6 +138,7 @@ static inline unsigned int compute_cas_write_latency(void)
}
return cwl;
}
+#endif
/* Chip Select Configuration (CSn_CONFIG) */
static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
@@ -135,6 +155,11 @@ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
int go_config = 0;
+#ifdef CONFIG_SYS_FSL_DDR4
+ unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
+#else
+ unsigned int n_banks_per_sdram_device;
+#endif
/* Compute CS_CONFIG only for existing ranks of each DIMM. */
switch (i) {
@@ -178,14 +203,18 @@ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
break;
}
if (go_config) {
- unsigned int n_banks_per_sdram_device;
cs_n_en = 1;
ap_n_en = popts->cs_local_opts[i].auto_precharge;
odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
+#ifdef CONFIG_SYS_FSL_DDR4
+ ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
+ bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
+#else
n_banks_per_sdram_device
= dimm_params[dimm_number].n_banks_per_sdram_device;
ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
+#endif
row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
}
@@ -203,6 +232,9 @@ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
| ((ba_bits_cs_n & 0x3) << 14)
| ((row_bits_cs_n & 0x7) << 8)
+#ifdef CONFIG_SYS_FSL_DDR4
+ | ((bg_bits_cs_n & 0x3) << 4)
+#endif
| ((col_bits_cs_n & 0x7) << 0)
);
debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
@@ -262,11 +294,23 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
/* Precharge powerdown exit timing (tXP). */
unsigned char pre_pd_exit_mclk;
/* ODT powerdown exit timing (tAXPD). */
- unsigned char taxpd_mclk;
+ unsigned char taxpd_mclk = 0;
/* Mode register set cycle time (tMRD). */
unsigned char tmrd_mclk;
-#ifdef CONFIG_SYS_FSL_DDR3
+#ifdef CONFIG_SYS_FSL_DDR4
+ /* tXP=max(4nCK, 6ns) */
+ int txp = max((get_memory_clk_period_ps() * 4), 6000); /* unit=ps */
+ trwt_mclk = 2;
+ twrt_mclk = 1;
+ act_pd_exit_mclk = picos_to_mclk(txp);
+ pre_pd_exit_mclk = act_pd_exit_mclk;
+ /*
+ * MRS_CYC = max(tMRD, tMOD)
+ * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
+ */
+ tmrd_mclk = max(24, picos_to_mclk(15000));
+#elif defined(CONFIG_SYS_FSL_DDR3)
/*
* (tXARD and tXARDS). Empirical?
* The DDR3 spec has not tXARD,
@@ -275,7 +319,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
* spec has not the tAXPD, we use
* tAXPD=1, need design to confirm.
*/
- int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
+ int txp = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
unsigned int data_rate = get_ddr_freq(0);
tmrd_mclk = 4;
/* set the turnaround time */
@@ -300,7 +344,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
taxpd_mclk = 1;
} else {
/* act_pd_exit_mclk = tXARD, see above */
- act_pd_exit_mclk = picos_to_mclk(tXP);
+ act_pd_exit_mclk = picos_to_mclk(txp);
/* Mode register MR0[A12] is '1' - fast exit */
pre_pd_exit_mclk = act_pd_exit_mclk;
taxpd_mclk = 1;
@@ -364,8 +408,12 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
ext_caslat = (2 * cas_latency - 1) >> 4;
ext_add_lat = additive_latency >> 4;
+#ifdef CONFIG_SYS_FSL_DDR4
+ ext_refrec = (picos_to_mclk(common_dimm->trfc1_ps) - 8) >> 4;
+#else
ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
/* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
+#endif
ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
(popts->otf_burst_chop_en ? 2 : 0)) >> 4;
@@ -404,9 +452,19 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
unsigned char acttoact_mclk;
/* Last write data pair to read command issue interval (tWTR) */
unsigned char wrtord_mclk;
+#ifdef CONFIG_SYS_FSL_DDR4
+ /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
+ static const u8 wrrec_table[] = {
+ 10, 10, 10, 10, 10,
+ 10, 10, 10, 10, 10,
+ 12, 12, 14, 14, 16,
+ 16, 18, 18, 20, 20,
+ 24, 24, 24, 24};
+#else
/* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
static const u8 wrrec_table[] = {
1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
+#endif
pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
@@ -438,20 +496,34 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
* we need set extend bit for it at
* TIMING_CFG_3[EXT_CASLAT]
*/
- caslat_ctrl = 2 * cas_latency - 1;
+ if (fsl_ddr_get_version() <= 0x40400)
+ caslat_ctrl = 2 * cas_latency - 1;
+ else
+ caslat_ctrl = (cas_latency - 1) << 1;
#endif
+#ifdef CONFIG_SYS_FSL_DDR4
+ refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8;
+ wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
+ acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4);
+ wrtord_mclk = max(2, picos_to_mclk(2500));
+ if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
+ printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
+ else
+ wrrec_mclk = wrrec_table[wrrec_mclk - 1];
+#else
refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
-
- if (wrrec_mclk > 16)
- printf("Error: WRREC doesn't support more than 16 clocks\n");
+ acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
+ wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
+ if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
+ printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
else
wrrec_mclk = wrrec_table[wrrec_mclk - 1];
+#endif
if (popts->otf_burst_chop_en)
wrrec_mclk += 2;
- acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
/*
* JEDEC has min requirement for tRRD
*/
@@ -459,7 +531,6 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
if (acttoact_mclk < 4)
acttoact_mclk = 4;
#endif
- wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
/*
* JEDEC has some min requirements for tWTR
*/
@@ -526,14 +597,18 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
wr_lat = compute_cas_write_latency();
#endif
+#ifdef CONFIG_SYS_FSL_DDR4
+ rd_to_pre = picos_to_mclk(7500);
+#else
rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
+#endif
/*
* JEDEC has some min requirements for tRTP
*/
#if defined(CONFIG_SYS_FSL_DDR2)
if (rd_to_pre < 2)
rd_to_pre = 2;
-#elif defined(CONFIG_SYS_FSL_DDR3)
+#elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
if (rd_to_pre < 4)
rd_to_pre = 4;
#endif
@@ -541,13 +616,20 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
rd_to_pre += 2; /* according to UM */
wr_data_delay = popts->write_data_delay;
+#ifdef CONFIG_SYS_FSL_DDR4
+ cpo = 0;
+ cke_pls = max(3, picos_to_mclk(5000));
+#else
cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps);
+#endif
+
four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
ddr->timing_cfg_2 = (0
| ((add_lat_mclk & 0xf) << 28)
| ((cpo & 0x1f) << 23)
| ((wr_lat & 0xf) << 19)
+ | ((wr_lat & 0x10) << 14)
| ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
| ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
| ((cke_pls & 0x7) << 6)
@@ -640,7 +722,8 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
* we must clear it when use the on-the-fly mode,
* must set it when use the 32-bits bus mode.
*/
- if (sdram_type == SDRAM_TYPE_DDR3) {
+ if ((sdram_type == SDRAM_TYPE_DDR3) ||
+ (sdram_type == SDRAM_TYPE_DDR4)) {
if (popts->burst_length == DDR_BL8)
eight_be = 1;
if (popts->burst_length == DDR_OTF)
@@ -682,8 +765,6 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
{
unsigned int frc_sr = 0; /* Force self refresh */
unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
- unsigned int dll_rst_dis; /* DLL reset disable */
- unsigned int dqs_cfg; /* DQS configuration */
unsigned int odt_cfg = 0; /* ODT configuration */
unsigned int num_pr; /* Number of posted refreshes */
unsigned int slow = 0; /* DDR will be run less than 1250 */
@@ -695,9 +776,12 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
unsigned int md_en = 0; /* Mirrored DIMM Enable */
unsigned int qd_en = 0; /* quad-rank DIMM Enable */
int i;
+#ifndef CONFIG_SYS_FSL_DDR4
+ unsigned int dll_rst_dis = 1; /* DLL reset disable */
+ unsigned int dqs_cfg; /* DQS configuration */
- dll_rst_dis = 1; /* Make this configurable */
dqs_cfg = popts->dqs_config;
+#endif
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (popts->cs_local_opts[i].odt_rd_cfg
|| popts->cs_local_opts[i].odt_wr_cfg) {
@@ -715,7 +799,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
* * ({EXT_REFREC || REFREC} + 8 + 2)]}
* << DDR_SDRAM_INTERVAL[REFINT]
*/
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
obc_cfg = popts->otf_burst_chop_en;
#else
obc_cfg = 0;
@@ -744,15 +828,17 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
d_init = 0;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
md_en = popts->mirrored_dimm;
#endif
qd_en = popts->quad_rank_present ? 1 : 0;
ddr->ddr_sdram_cfg_2 = (0
| ((frc_sr & 0x1) << 31)
| ((sr_ie & 0x1) << 30)
+#ifndef CONFIG_SYS_FSL_DDR4
| ((dll_rst_dis & 0x1) << 29)
| ((dqs_cfg & 0x3) << 26)
+#endif
| ((odt_cfg & 0x3) << 21)
| ((num_pr & 0xf) << 12)
| ((slow & 1) << 11)
@@ -768,6 +854,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
}
+#ifdef CONFIG_SYS_FSL_DDR4
/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
@@ -776,8 +863,93 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
{
unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
+ int i;
+ unsigned int wr_crc = 0; /* Disable */
+ unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
+ unsigned int srt = 0; /* self-refresh temerature, normal range */
+ unsigned int cwl = compute_cas_write_latency() - 9;
+ unsigned int mpr = 0; /* serial */
+ unsigned int wc_lat;
+ const unsigned int mclk_ps = get_memory_clk_period_ps();
-#if defined(CONFIG_SYS_FSL_DDR3)
+ if (popts->rtt_override)
+ rtt_wr = popts->rtt_wr_override_value;
+ else
+ rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
+
+ if (common_dimm->extended_op_srt)
+ srt = common_dimm->extended_op_srt;
+
+ esdmode2 = (0
+ | ((wr_crc & 0x1) << 12)
+ | ((rtt_wr & 0x3) << 9)
+ | ((srt & 0x3) << 6)
+ | ((cwl & 0x7) << 3));
+
+ if (mclk_ps >= 1250)
+ wc_lat = 0;
+ else if (mclk_ps >= 833)
+ wc_lat = 1;
+ else
+ wc_lat = 2;
+
+ esdmode3 = (0
+ | ((mpr & 0x3) << 11)
+ | ((wc_lat & 0x3) << 9));
+
+ ddr->ddr_sdram_mode_2 = (0
+ | ((esdmode2 & 0xFFFF) << 16)
+ | ((esdmode3 & 0xFFFF) << 0)
+ );
+ debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
+
+ if (unq_mrs_en) { /* unique mode registers are supported */
+ for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (popts->rtt_override)
+ rtt_wr = popts->rtt_wr_override_value;
+ else
+ rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
+
+ esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
+ esdmode2 |= (rtt_wr & 0x3) << 9;
+ switch (i) {
+ case 1:
+ ddr->ddr_sdram_mode_4 = (0
+ | ((esdmode2 & 0xFFFF) << 16)
+ | ((esdmode3 & 0xFFFF) << 0)
+ );
+ break;
+ case 2:
+ ddr->ddr_sdram_mode_6 = (0
+ | ((esdmode2 & 0xFFFF) << 16)
+ | ((esdmode3 & 0xFFFF) << 0)
+ );
+ break;
+ case 3:
+ ddr->ddr_sdram_mode_8 = (0
+ | ((esdmode2 & 0xFFFF) << 16)
+ | ((esdmode3 & 0xFFFF) << 0)
+ );
+ break;
+ }
+ }
+ debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
+ ddr->ddr_sdram_mode_4);
+ debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
+ ddr->ddr_sdram_mode_6);
+ debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
+ ddr->ddr_sdram_mode_8);
+ }
+}
+#elif defined(CONFIG_SYS_FSL_DDR3)
+/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
+static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm,
+ const unsigned int unq_mrs_en)
+{
+ unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
+ unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
int i;
unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
unsigned int srt = 0; /* self-refresh temerature, normal range */
@@ -799,14 +971,12 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
| ((asr & 0x1) << 6)
| ((cwl & 0x7) << 3)
| ((pasr & 0x7) << 0));
-#endif
ddr->ddr_sdram_mode_2 = (0
| ((esdmode2 & 0xFFFF) << 16)
| ((esdmode3 & 0xFFFF) << 0)
);
debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
-#ifdef CONFIG_SYS_FSL_DDR3
if (unq_mrs_en) { /* unique mode registers are supported */
for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (popts->rtt_override)
@@ -844,9 +1014,128 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
ddr->ddr_sdram_mode_8);
}
+}
+
+#else /* for DDR2 and DDR1 */
+/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
+static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm,
+ const unsigned int unq_mrs_en)
+{
+ unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
+ unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
+
+ ddr->ddr_sdram_mode_2 = (0
+ | ((esdmode2 & 0xFFFF) << 16)
+ | ((esdmode3 & 0xFFFF) << 0)
+ );
+ debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
+}
#endif
+
+#ifdef CONFIG_SYS_FSL_DDR4
+/* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
+static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm,
+ const unsigned int unq_mrs_en)
+{
+ int i;
+ unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */
+ unsigned short esdmode5; /* Extended SDRAM mode 5 */
+
+ esdmode5 = 0x00000400; /* Data mask enabled */
+
+ ddr->ddr_sdram_mode_9 = (0
+ | ((esdmode4 & 0xffff) << 16)
+ | ((esdmode5 & 0xffff) << 0)
+ );
+ debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
+ if (unq_mrs_en) { /* unique mode registers are supported */
+ for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ switch (i) {
+ case 1:
+ ddr->ddr_sdram_mode_11 = (0
+ | ((esdmode4 & 0xFFFF) << 16)
+ | ((esdmode5 & 0xFFFF) << 0)
+ );
+ break;
+ case 2:
+ ddr->ddr_sdram_mode_13 = (0
+ | ((esdmode4 & 0xFFFF) << 16)
+ | ((esdmode5 & 0xFFFF) << 0)
+ );
+ break;
+ case 3:
+ ddr->ddr_sdram_mode_15 = (0
+ | ((esdmode4 & 0xFFFF) << 16)
+ | ((esdmode5 & 0xFFFF) << 0)
+ );
+ break;
+ }
+ }
+ debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
+ ddr->ddr_sdram_mode_11);
+ debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
+ ddr->ddr_sdram_mode_13);
+ debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
+ ddr->ddr_sdram_mode_15);
+ }
+}
+
+/* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
+static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm,
+ const unsigned int unq_mrs_en)
+{
+ int i;
+ unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */
+ unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */
+ unsigned int tccdl_min = picos_to_mclk(common_dimm->tccdl_ps);
+
+ esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
+
+ ddr->ddr_sdram_mode_10 = (0
+ | ((esdmode6 & 0xffff) << 16)
+ | ((esdmode7 & 0xffff) << 0)
+ );
+ debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10);
+ if (unq_mrs_en) { /* unique mode registers are supported */
+ for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ switch (i) {
+ case 1:
+ ddr->ddr_sdram_mode_12 = (0
+ | ((esdmode6 & 0xFFFF) << 16)
+ | ((esdmode7 & 0xFFFF) << 0)
+ );
+ break;
+ case 2:
+ ddr->ddr_sdram_mode_14 = (0
+ | ((esdmode6 & 0xFFFF) << 16)
+ | ((esdmode7 & 0xFFFF) << 0)
+ );
+ break;
+ case 3:
+ ddr->ddr_sdram_mode_16 = (0
+ | ((esdmode6 & 0xFFFF) << 16)
+ | ((esdmode7 & 0xFFFF) << 0)
+ );
+ break;
+ }
+ }
+ debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
+ ddr->ddr_sdram_mode_12);
+ debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
+ ddr->ddr_sdram_mode_14);
+ debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
+ ddr->ddr_sdram_mode_16);
+ }
}
+#endif
+
/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
@@ -867,7 +1156,7 @@ static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
}
-#if defined(CONFIG_SYS_FSL_DDR3)
+#ifdef CONFIG_SYS_FSL_DDR4
/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
@@ -876,6 +1165,177 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
unsigned int additive_latency,
const unsigned int unq_mrs_en)
{
+ int i;
+ unsigned short esdmode; /* Extended SDRAM mode */
+ unsigned short sdmode; /* SDRAM mode */
+
+ /* Mode Register - MR1 */
+ unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
+ unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
+ unsigned int rtt;
+ unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
+ unsigned int al = 0; /* Posted CAS# additive latency (AL) */
+ unsigned int dic = 0; /* Output driver impedance, 40ohm */
+ unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal),
+ 0=Disable (Test/Debug) */
+
+ /* Mode Register - MR0 */
+ unsigned int wr = 0; /* Write Recovery */
+ unsigned int dll_rst; /* DLL Reset */
+ unsigned int mode; /* Normal=0 or Test=1 */
+ unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
+ /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
+ unsigned int bt;
+ unsigned int bl; /* BL: Burst Length */
+
+ unsigned int wr_mclk;
+ /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
+ static const u8 wr_table[] = {
+ 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
+ /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
+ static const u8 cas_latency_table[] = {
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
+ 9, 9, 10, 10, 11, 11};
+
+ if (popts->rtt_override)
+ rtt = popts->rtt_override_value;
+ else
+ rtt = popts->cs_local_opts[0].odt_rtt_norm;
+
+ if (additive_latency == (cas_latency - 1))
+ al = 1;
+ if (additive_latency == (cas_latency - 2))
+ al = 2;
+
+ if (popts->quad_rank_present)
+ dic = 1; /* output driver impedance 240/7 ohm */
+
+ /*
+ * The esdmode value will also be used for writing
+ * MR1 during write leveling for DDR3, although the
+ * bits specifically related to the write leveling
+ * scheme will be handled automatically by the DDR
+ * controller. so we set the wrlvl_en = 0 here.
+ */
+ esdmode = (0
+ | ((qoff & 0x1) << 12)
+ | ((tdqs_en & 0x1) << 11)
+ | ((rtt & 0x7) << 8)
+ | ((wrlvl_en & 0x1) << 7)
+ | ((al & 0x3) << 3)
+ | ((dic & 0x3) << 1) /* DIC field is split */
+ | ((dll_en & 0x1) << 0)
+ );
+
+ /*
+ * DLL control for precharge PD
+ * 0=slow exit DLL off (tXPDLL)
+ * 1=fast exit DLL on (tXP)
+ */
+
+ wr_mclk = picos_to_mclk(common_dimm->twr_ps);
+ if (wr_mclk <= 24) {
+ wr = wr_table[wr_mclk - 10];
+ } else {
+ printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
+ wr_mclk);
+ }
+
+ dll_rst = 0; /* dll no reset */
+ mode = 0; /* normal mode */
+
+ /* look up table to get the cas latency bits */
+ if (cas_latency >= 9 && cas_latency <= 24)
+ caslat = cas_latency_table[cas_latency - 9];
+ else
+ printf("Error: unsupported cas latency for mode register\n");
+
+ bt = 0; /* Nibble sequential */
+
+ switch (popts->burst_length) {
+ case DDR_BL8:
+ bl = 0;
+ break;
+ case DDR_OTF:
+ bl = 1;
+ break;
+ case DDR_BC4:
+ bl = 2;
+ break;
+ default:
+ printf("Error: invalid burst length of %u specified. ",
+ popts->burst_length);
+ puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
+ bl = 1;
+ break;
+ }
+
+ sdmode = (0
+ | ((wr & 0x7) << 9)
+ | ((dll_rst & 0x1) << 8)
+ | ((mode & 0x1) << 7)
+ | (((caslat >> 1) & 0x7) << 4)
+ | ((bt & 0x1) << 3)
+ | ((caslat & 1) << 2)
+ | ((bl & 0x3) << 0)
+ );
+
+ ddr->ddr_sdram_mode = (0
+ | ((esdmode & 0xFFFF) << 16)
+ | ((sdmode & 0xFFFF) << 0)
+ );
+
+ debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
+
+ if (unq_mrs_en) { /* unique mode registers are supported */
+ for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (popts->rtt_override)
+ rtt = popts->rtt_override_value;
+ else
+ rtt = popts->cs_local_opts[i].odt_rtt_norm;
+
+ esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */
+ esdmode |= (rtt & 0x7) << 8;
+ switch (i) {
+ case 1:
+ ddr->ddr_sdram_mode_3 = (0
+ | ((esdmode & 0xFFFF) << 16)
+ | ((sdmode & 0xFFFF) << 0)
+ );
+ break;
+ case 2:
+ ddr->ddr_sdram_mode_5 = (0
+ | ((esdmode & 0xFFFF) << 16)
+ | ((sdmode & 0xFFFF) << 0)
+ );
+ break;
+ case 3:
+ ddr->ddr_sdram_mode_7 = (0
+ | ((esdmode & 0xFFFF) << 16)
+ | ((sdmode & 0xFFFF) << 0)
+ );
+ break;
+ }
+ }
+ debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
+ ddr->ddr_sdram_mode_3);
+ debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
+ ddr->ddr_sdram_mode_5);
+ debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
+ ddr->ddr_sdram_mode_5);
+ }
+}
+
+#elif defined(CONFIG_SYS_FSL_DDR3)
+/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
+static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm,
+ unsigned int cas_latency,
+ unsigned int additive_latency,
+ const unsigned int unq_mrs_en)
+{
+ int i;
unsigned short esdmode; /* Extended SDRAM mode */
unsigned short sdmode; /* SDRAM mode */
@@ -907,9 +1367,6 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
*/
static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
- const unsigned int mclk_ps = get_memory_clk_period_ps();
- int i;
-
if (popts->rtt_override)
rtt = popts->rtt_override_value;
else
@@ -950,7 +1407,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
*/
dll_on = 1;
- wr_mclk = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps;
+ wr_mclk = picos_to_mclk(common_dimm->twr_ps);
if (wr_mclk <= 16) {
wr = wr_table[wr_mclk - 5];
} else {
@@ -1109,9 +1566,6 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
unsigned int bt;
unsigned int bl; /* BL: Burst Length */
-#if defined(CONFIG_SYS_FSL_DDR2)
- const unsigned int mclk_ps = get_memory_clk_period_ps();
-#endif
dqs_en = !popts->dqs_config;
rtt = fsl_ddr_get_rtt();
@@ -1141,7 +1595,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
#if defined(CONFIG_SYS_FSL_DDR1)
wr = 0; /* Historical */
#elif defined(CONFIG_SYS_FSL_DDR2)
- wr = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps - 1;
+ wr = picos_to_mclk(common_dimm->twr_ps);
#endif
dll_res = 0;
mode = 0;
@@ -1255,7 +1709,7 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
if (popts->burst_length == DDR_BL8) {
/* We set BL/2 for fixed BL8 */
rrt = 0; /* BL/2 clocks */
@@ -1265,6 +1719,11 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
rrt = 2; /* BL/2 + 2 clocks */
wwt = 2; /* BL/2 + 2 clocks */
}
+#endif
+
+#ifdef CONFIG_SYS_FSL_DDR4
+ dll_lock = 2; /* tDLLK = 1024 clocks */
+#elif defined(CONFIG_SYS_FSL_DDR3)
dll_lock = 1; /* tDLLK = 512 clocks from spec */
#endif
ddr->timing_cfg_4 = (0
@@ -1285,9 +1744,12 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
unsigned int wodt_on = 0; /* Write to ODT on */
unsigned int wodt_off = 0; /* Write to ODT off */
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
+ unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
+ ((ddr->timing_cfg_2 & 0x00040000) >> 14);
/* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
- rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
+ if (cas_latency >= wr_lat)
+ rodt_on = cas_latency - wr_lat + 1;
rodt_off = 4; /* 4 clocks */
wodt_on = 1; /* 1 clocks */
wodt_off = 4; /* 4 clocks */
@@ -1302,6 +1764,164 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
}
+#ifdef CONFIG_SYS_FSL_DDR4
+static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
+{
+ unsigned int hs_caslat = 0;
+ unsigned int hs_wrlat = 0;
+ unsigned int hs_wrrec = 0;
+ unsigned int hs_clkadj = 0;
+ unsigned int hs_wrlvl_start = 0;
+
+ ddr->timing_cfg_6 = (0
+ | ((hs_caslat & 0x1f) << 24)
+ | ((hs_wrlat & 0x1f) << 19)
+ | ((hs_wrrec & 0x1f) << 12)
+ | ((hs_clkadj & 0x1f) << 6)
+ | ((hs_wrlvl_start & 0x1f) << 0)
+ );
+ debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
+}
+
+static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr,
+ const common_timing_params_t *common_dimm)
+{
+ unsigned int txpr, tcksre, tcksrx;
+ unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
+
+ txpr = max(5, picos_to_mclk(common_dimm->trfc1_ps + 10000));
+ tcksre = max(5, picos_to_mclk(10000));
+ tcksrx = max(5, picos_to_mclk(10000));
+ par_lat = 0;
+ cs_to_cmd = 0;
+
+ if (txpr <= 200)
+ cke_rst = 0;
+ else if (txpr <= 256)
+ cke_rst = 1;
+ else if (txpr <= 512)
+ cke_rst = 2;
+ else
+ cke_rst = 3;
+
+ if (tcksre <= 19)
+ cksre = tcksre - 5;
+ else
+ cksre = 15;
+
+ if (tcksrx <= 19)
+ cksrx = tcksrx - 5;
+ else
+ cksrx = 15;
+
+ ddr->timing_cfg_7 = (0
+ | ((cke_rst & 0x3) << 28)
+ | ((cksre & 0xf) << 24)
+ | ((cksrx & 0xf) << 20)
+ | ((par_lat & 0xf) << 16)
+ | ((cs_to_cmd & 0xf) << 4)
+ );
+ debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
+}
+
+static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm,
+ unsigned int cas_latency)
+{
+ unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
+ unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
+ unsigned int tccdl = picos_to_mclk(common_dimm->tccdl_ps);
+ unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
+ ((ddr->timing_cfg_2 & 0x00040000) >> 14);
+
+ rwt_bg = cas_latency + 2 + 4 - wr_lat;
+ if (rwt_bg < tccdl)
+ rwt_bg = tccdl - rwt_bg;
+ else
+ rwt_bg = 0;
+
+ wrt_bg = wr_lat + 4 + 1 - cas_latency;
+ if (wrt_bg < tccdl)
+ wrt_bg = tccdl - wrt_bg;
+ else
+ wrt_bg = 0;
+
+ if (popts->burst_length == DDR_BL8) {
+ rrt_bg = tccdl - 4;
+ wwt_bg = tccdl - 4;
+ } else {
+ rrt_bg = tccdl - 2;
+ wwt_bg = tccdl - 4;
+ }
+
+ acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
+ wrtord_bg = max(4, picos_to_mclk(7500));
+ pre_all_rec = 0;
+
+ ddr->timing_cfg_8 = (0
+ | ((rwt_bg & 0xf) << 28)
+ | ((wrt_bg & 0xf) << 24)
+ | ((rrt_bg & 0xf) << 20)
+ | ((wwt_bg & 0xf) << 16)
+ | ((acttoact_bg & 0xf) << 12)
+ | ((wrtord_bg & 0xf) << 8)
+ | ((pre_all_rec & 0x1f) << 0)
+ );
+
+ debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
+}
+
+static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
+{
+ ddr->timing_cfg_9 = 0;
+ debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
+}
+
+static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
+ const dimm_params_t *dimm_params)
+{
+ ddr->dq_map_0 = ((dimm_params->dq_mapping[0] & 0x3F) << 26) |
+ ((dimm_params->dq_mapping[1] & 0x3F) << 20) |
+ ((dimm_params->dq_mapping[2] & 0x3F) << 14) |
+ ((dimm_params->dq_mapping[3] & 0x3F) << 8) |
+ ((dimm_params->dq_mapping[4] & 0x3F) << 2);
+
+ ddr->dq_map_1 = ((dimm_params->dq_mapping[5] & 0x3F) << 26) |
+ ((dimm_params->dq_mapping[6] & 0x3F) << 20) |
+ ((dimm_params->dq_mapping[7] & 0x3F) << 14) |
+ ((dimm_params->dq_mapping[10] & 0x3F) << 8) |
+ ((dimm_params->dq_mapping[11] & 0x3F) << 2);
+
+ ddr->dq_map_2 = ((dimm_params->dq_mapping[12] & 0x3F) << 26) |
+ ((dimm_params->dq_mapping[13] & 0x3F) << 20) |
+ ((dimm_params->dq_mapping[14] & 0x3F) << 14) |
+ ((dimm_params->dq_mapping[15] & 0x3F) << 8) |
+ ((dimm_params->dq_mapping[16] & 0x3F) << 2);
+
+ ddr->dq_map_3 = ((dimm_params->dq_mapping[17] & 0x3F) << 26) |
+ ((dimm_params->dq_mapping[8] & 0x3F) << 20) |
+ ((dimm_params->dq_mapping[9] & 0x3F) << 14) |
+ dimm_params->dq_mapping_ors;
+
+ debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
+ debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
+ debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
+ debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
+}
+static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts)
+{
+ int rd_pre;
+
+ rd_pre = popts->quad_rank_present ? 1 : 0;
+
+ ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
+
+ debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
+}
+#endif /* CONFIG_SYS_FSL_DDR4 */
+
/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
{
@@ -1310,11 +1930,21 @@ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
unsigned int zqoper = 0;
/* Normal Operation Short Calibration Time (tZQCS) */
unsigned int zqcs = 0;
+#ifdef CONFIG_SYS_FSL_DDR4
+ unsigned int zqcs_init;
+#endif
if (zq_en) {
+#ifdef CONFIG_SYS_FSL_DDR4
+ zqinit = 10; /* 1024 clocks */
+ zqoper = 9; /* 512 clocks */
+ zqcs = 7; /* 128 clocks */
+ zqcs_init = 5; /* 1024 refresh sequences */
+#else
zqinit = 9; /* 512 clocks */
zqoper = 8; /* 256 clocks */
zqcs = 6; /* 64 clocks */
+#endif
}
ddr->ddr_zq_cntl = (0
@@ -1322,6 +1952,9 @@ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
| ((zqinit & 0xF) << 24)
| ((zqoper & 0xF) << 16)
| ((zqcs & 0xF) << 8)
+#ifdef CONFIG_SYS_FSL_DDR4
+ | ((zqcs_init & 0xF) << 0)
+#endif
);
debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
}
@@ -1478,7 +2111,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
*/
cas_latency = (popts->cas_latency_override)
? popts->cas_latency_override_value
- : common_dimm->lowest_common_SPD_caslat;
+ : common_dimm->lowest_common_spd_caslat;
additive_latency = (popts->additive_latency_override)
? popts->additive_latency_override_value
@@ -1639,6 +2272,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
set_ddr_sdram_mode(ddr, popts, common_dimm,
cas_latency, additive_latency, unq_mrs_en);
set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
+#ifdef CONFIG_SYS_FSL_DDR4
+ set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
+ set_ddr_sdram_mode_10(ddr, popts, common_dimm, unq_mrs_en);
+#endif
set_ddr_sdram_interval(ddr, popts, common_dimm);
set_ddr_data_init(ddr);
set_ddr_sdram_clk_cntl(ddr, popts);
@@ -1646,6 +2283,14 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
set_ddr_init_ext_addr(ddr);
set_timing_cfg_4(ddr, popts);
set_timing_cfg_5(ddr, cas_latency);
+#ifdef CONFIG_SYS_FSL_DDR4
+ set_ddr_sdram_cfg_3(ddr, popts);
+ set_timing_cfg_6(ddr);
+ set_timing_cfg_7(ddr, common_dimm);
+ set_timing_cfg_8(ddr, popts, common_dimm, cas_latency);
+ set_timing_cfg_9(ddr);
+ set_ddr_dq_mapping(ddr, dimm_params);
+#endif
set_ddr_zq_cntl(ddr, zq_en);
set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c
new file mode 100644
index 0000000..4745b7f
--- /dev/null
+++ b/drivers/ddr/fsl/ddr4_dimm_params.c
@@ -0,0 +1,300 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * calculate the organization and timing parameter
+ * from ddr3 spd, please refer to the spec
+ * JEDEC standard No.21-C 4_01_02_12R23A.pdf
+ *
+ *
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+
+#include <fsl_ddr.h>
+
+/*
+ * Calculate the Density of each Physical Rank.
+ * Returned size is in bytes.
+ *
+ * Total DIMM size =
+ * sdram capacity(bit) / 8 * primary bus width / sdram width
+ * * Logical Ranks per DIMM
+ *
+ * where: sdram capacity = spd byte4[3:0]
+ * primary bus width = spd byte13[2:0]
+ * sdram width = spd byte12[2:0]
+ * Logical Ranks per DIMM = spd byte12[5:3] for SDP, DDP, QDP
+ * spd byte12{5:3] * spd byte6[6:4] for 3DS
+ *
+ * To simplify each rank size = total DIMM size / Number of Package Ranks
+ * where Number of Package Ranks = spd byte12[5:3]
+ *
+ * SPD byte4 - sdram density and banks
+ * bit[3:0] size(bit) size(byte)
+ * 0000 256Mb 32MB
+ * 0001 512Mb 64MB
+ * 0010 1Gb 128MB
+ * 0011 2Gb 256MB
+ * 0100 4Gb 512MB
+ * 0101 8Gb 1GB
+ * 0110 16Gb 2GB
+ * 0111 32Gb 4GB
+ *
+ * SPD byte13 - module memory bus width
+ * bit[2:0] primary bus width
+ * 000 8bits
+ * 001 16bits
+ * 010 32bits
+ * 011 64bits
+ *
+ * SPD byte12 - module organization
+ * bit[2:0] sdram device width
+ * 000 4bits
+ * 001 8bits
+ * 010 16bits
+ * 011 32bits
+ *
+ * SPD byte12 - module organization
+ * bit[5:3] number of package ranks per DIMM
+ * 000 1
+ * 001 2
+ * 010 3
+ * 011 4
+ *
+ * SPD byte6 - SDRAM package type
+ * bit[6:4] Die count
+ * 000 1
+ * 001 2
+ * 010 3
+ * 011 4
+ * 100 5
+ * 101 6
+ * 110 7
+ * 111 8
+ *
+ * SPD byte6 - SRAM package type
+ * bit[1:0] Signal loading
+ * 00 Not specified
+ * 01 Multi load stack
+ * 10 Sigle load stack (3DS)
+ * 11 Reserved
+ */
+static unsigned long long
+compute_ranksize(const struct ddr4_spd_eeprom_s *spd)
+{
+ unsigned long long bsize;
+
+ int nbit_sdram_cap_bsize = 0;
+ int nbit_primary_bus_width = 0;
+ int nbit_sdram_width = 0;
+ int die_count = 0;
+ bool package_3ds;
+
+ if ((spd->density_banks & 0xf) <= 7)
+ nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
+ if ((spd->bus_width & 0x7) < 4)
+ nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
+ if ((spd->organization & 0x7) < 4)
+ nbit_sdram_width = (spd->organization & 0x7) + 2;
+ package_3ds = (spd->package_type & 0x3) == 0x2;
+ if (package_3ds)
+ die_count = (spd->package_type >> 4) & 0x7;
+
+ bsize = 1ULL << (nbit_sdram_cap_bsize - 3 +
+ nbit_primary_bus_width - nbit_sdram_width +
+ die_count);
+
+ debug("DDR: DDR III rank density = 0x%16llx\n", bsize);
+
+ return bsize;
+}
+
+#define spd_to_ps(mtb, ftb) \
+ (mtb * pdimm->mtb_ps + (ftb * pdimm->ftb_10th_ps) / 10)
+/*
+ * ddr_compute_dimm_parameters for DDR3 SPD
+ *
+ * Compute DIMM parameters based upon the SPD information in spd.
+ * Writes the results to the dimm_params_t structure pointed by pdimm.
+ *
+ */
+unsigned int
+ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd,
+ dimm_params_t *pdimm,
+ unsigned int dimm_number)
+{
+ unsigned int retval;
+ int i;
+
+ if (spd->mem_type) {
+ if (spd->mem_type != SPD_MEMTYPE_DDR4) {
+ printf("DIMM %u: is not a DDR4 SPD.\n", dimm_number);
+ return 1;
+ }
+ } else {
+ memset(pdimm, 0, sizeof(dimm_params_t));
+ return 1;
+ }
+
+ retval = ddr4_spd_check(spd);
+ if (retval) {
+ printf("DIMM %u: failed checksum\n", dimm_number);
+ return 2;
+ }
+
+ /*
+ * The part name in ASCII in the SPD EEPROM is not null terminated.
+ * Guarantee null termination here by presetting all bytes to 0
+ * and copying the part name in ASCII from the SPD onto it
+ */
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ if ((spd->info_size_crc & 0xF) > 2)
+ memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
+
+ /* DIMM organization parameters */
+ pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
+ pdimm->rank_density = compute_ranksize(spd);
+ pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
+ pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
+ if ((spd->bus_width >> 3) & 0x3)
+ pdimm->ec_sdram_width = 8;
+ else
+ pdimm->ec_sdram_width = 0;
+ pdimm->data_width = pdimm->primary_sdram_width
+ + pdimm->ec_sdram_width;
+ pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
+
+ /* These are the types defined by the JEDEC DDR3 SPD spec */
+ pdimm->mirrored_dimm = 0;
+ pdimm->registered_dimm = 0;
+ switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) {
+ case DDR3_SPD_MODULETYPE_RDIMM:
+ /* Registered/buffered DIMMs */
+ pdimm->registered_dimm = 1;
+ break;
+
+ case DDR3_SPD_MODULETYPE_UDIMM:
+ case DDR3_SPD_MODULETYPE_SO_DIMM:
+ /* Unbuffered DIMMs */
+ if (spd->mod_section.unbuffered.addr_mapping & 0x1)
+ pdimm->mirrored_dimm = 1;
+ break;
+
+ default:
+ printf("unknown module_type 0x%02X\n", spd->module_type);
+ return 1;
+ }
+
+ /* SDRAM device parameters */
+ pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
+ pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
+ pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3;
+ pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3;
+
+ /*
+ * The SPD spec has not the ECC bit,
+ * We consider the DIMM as ECC capability
+ * when the extension bus exist
+ */
+ if (pdimm->ec_sdram_width)
+ pdimm->edc_config = 0x02;
+ else
+ pdimm->edc_config = 0x00;
+
+ /*
+ * The SPD spec has not the burst length byte
+ * but DDR4 spec has nature BL8 and BC4,
+ * BL8 -bit3, BC4 -bit2
+ */
+ pdimm->burst_lengths_bitmask = 0x0c;
+ pdimm->row_density = __ilog2(pdimm->rank_density);
+
+ /* MTB - medium timebase
+ * The MTB in the SPD spec is 125ps,
+ *
+ * FTB - fine timebase
+ * use 1/10th of ps as our unit to avoid floating point
+ * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
+ */
+ if ((spd->timebases & 0xf) == 0x0) {
+ pdimm->mtb_ps = 125;
+ pdimm->ftb_10th_ps = 10;
+
+ } else {
+ printf("Unknown Timebases\n");
+ }
+
+ /* sdram minimum cycle time */
+ pdimm->tckmin_x_ps = spd_to_ps(spd->tck_min, spd->fine_tck_min);
+
+ /* sdram max cycle time */
+ pdimm->tckmax_ps = spd_to_ps(spd->tck_max, spd->fine_tck_max);
+
+ /*
+ * CAS latency supported
+ * bit0 - CL7
+ * bit4 - CL11
+ * bit8 - CL15
+ * bit12- CL19
+ * bit16- CL23
+ */
+ pdimm->caslat_x = (spd->caslat_b1 << 7) |
+ (spd->caslat_b2 << 15) |
+ (spd->caslat_b3 << 23);
+
+ BUG_ON(spd->caslat_b4 != 0);
+
+ /*
+ * min CAS latency time
+ */
+ pdimm->taa_ps = spd_to_ps(spd->taa_min, spd->fine_taa_min);
+
+ /*
+ * min RAS to CAS delay time
+ */
+ pdimm->trcd_ps = spd_to_ps(spd->trcd_min, spd->fine_trcd_min);
+
+ /*
+ * Min Row Precharge Delay Time
+ */
+ pdimm->trp_ps = spd_to_ps(spd->trp_min, spd->fine_trp_min);
+
+ /* min active to precharge delay time */
+ pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) +
+ spd->tras_min_lsb) * pdimm->mtb_ps;
+
+ /* min active to actice/refresh delay time */
+ pdimm->trc_ps = spd_to_ps((((spd->tras_trc_ext & 0xf0) << 4) +
+ spd->trc_min_lsb), spd->fine_trc_min);
+ /* Min Refresh Recovery Delay Time */
+ pdimm->trfc1_ps = ((spd->trfc1_min_msb << 8) | (spd->trfc1_min_lsb)) *
+ pdimm->mtb_ps;
+ pdimm->trfc2_ps = ((spd->trfc2_min_msb << 8) | (spd->trfc2_min_lsb)) *
+ pdimm->mtb_ps;
+ pdimm->trfc4_ps = ((spd->trfc4_min_msb << 8) | (spd->trfc4_min_lsb)) *
+ pdimm->mtb_ps;
+ /* min four active window delay time */
+ pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) *
+ pdimm->mtb_ps;
+
+ /* min row active to row active delay time, different bank group */
+ pdimm->trrds_ps = spd_to_ps(spd->trrds_min, spd->fine_trrds_min);
+ /* min row active to row active delay time, same bank group */
+ pdimm->trrdl_ps = spd_to_ps(spd->trrdl_min, spd->fine_trrdl_min);
+ /* min CAS to CAS Delay Time (tCCD_Lmin), same bank group */
+ pdimm->tccdl_ps = spd_to_ps(spd->tccdl_min, spd->fine_tccdl_min);
+
+ /*
+ * Average periodic refresh interval
+ * tREFI = 7.8 us at normal temperature range
+ */
+ pdimm->refresh_rate_ps = 7800000;
+
+ for (i = 0; i < 18; i++)
+ pdimm->dq_mapping[i] = spd->mapping[i];
+
+ pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0;
+
+ return 0;
+}
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
new file mode 100644
index 0000000..7cd878a
--- /dev/null
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/processor.h>
+#include <fsl_ddr.h>
+
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
+#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
+#endif
+
+/*
+ * regs has the to-be-set values for DDR controller registers
+ * ctrl_num is the DDR controller number
+ * step: 0 goes through the initialization in one pass
+ * 1 sets registers and returns before enabling controller
+ * 2 resumes from step 1 and continues to initialize
+ * Dividing the initialization to two steps to deassert DDR reset signal
+ * to comply with JEDEC specs for RDIMMs.
+ */
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+ unsigned int ctrl_num, int step)
+{
+ unsigned int i, bus_width;
+ struct ccsr_ddr __iomem *ddr;
+ u32 temp_sdram_cfg;
+ u32 total_gb_size_per_controller;
+ int timeout;
+
+ switch (ctrl_num) {
+ case 0:
+ ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ break;
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+ case 1:
+ ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+ case 2:
+ ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+ case 3:
+ ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
+ break;
+#endif
+ default:
+ printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
+ return;
+ }
+
+ if (step == 2)
+ goto step2;
+
+ if (regs->ddr_eor)
+ ddr_out32(&ddr->eor, regs->ddr_eor);
+
+ ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
+
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (i == 0) {
+ ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
+ ddr_out32(&ddr->cs0_config, regs->cs[i].config);
+ ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
+
+ } else if (i == 1) {
+ ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
+ ddr_out32(&ddr->cs1_config, regs->cs[i].config);
+ ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
+
+ } else if (i == 2) {
+ ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
+ ddr_out32(&ddr->cs2_config, regs->cs[i].config);
+ ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
+
+ } else if (i == 3) {
+ ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
+ ddr_out32(&ddr->cs3_config, regs->cs[i].config);
+ ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
+ }
+ }
+
+ ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
+ ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
+ ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
+ ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
+ ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
+ ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
+ ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
+ ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
+ ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
+ ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
+ ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
+ ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
+ ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
+ ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
+ ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
+ ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+ ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
+ ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
+ ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
+ ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
+ ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
+ ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
+ ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
+ ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
+ ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
+ ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
+ ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
+ ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
+ ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
+ ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
+ ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
+ ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
+ ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
+ ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
+ ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+ ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
+ ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
+ ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+ ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
+#ifndef CONFIG_SYS_FSL_DDR_EMU
+ /*
+ * Skip these two registers if running on emulator
+ * because emulator doesn't have skew between bytes.
+ */
+
+ if (regs->ddr_wrlvl_cntl_2)
+ ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
+ if (regs->ddr_wrlvl_cntl_3)
+ ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
+#endif
+
+ ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
+ ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
+ ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
+ ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
+ ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
+ ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
+ ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
+ ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
+ ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+ ddr_out32(&ddr->err_disable, regs->err_disable);
+ ddr_out32(&ddr->err_int_en, regs->err_int_en);
+ for (i = 0; i < 32; i++) {
+ if (regs->debug[i]) {
+ debug("Write to debug_%d as %08x\n",
+ i+1, regs->debug[i]);
+ ddr_out32(&ddr->debug[i], regs->debug[i]);
+ }
+ }
+
+ /*
+ * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
+ * deasserted. Clocks start when any chip select is enabled and clock
+ * control register is set. Because all DDR components are connected to
+ * one reset signal, this needs to be done in two steps. Step 1 is to
+ * get the clocks started. Step 2 resumes after reset signal is
+ * deasserted.
+ */
+ if (step == 1) {
+ udelay(200);
+ return;
+ }
+
+step2:
+ /* Set, but do not enable the memory */
+ temp_sdram_cfg = regs->ddr_sdram_cfg;
+ temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
+ ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
+
+ /*
+ * 500 painful micro-seconds must elapse between
+ * the DDR clock setup and the DDR config enable.
+ * DDR2 need 200 us, and DDR3 need 500 us from spec,
+ * we choose the max, that is 500 us for all of case.
+ */
+ udelay(500);
+ asm volatile("sync;isync");
+
+ /* Let the controller go */
+ temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
+ ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
+ asm volatile("sync;isync");
+
+ total_gb_size_per_controller = 0;
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (!(regs->cs[i].config & 0x80000000))
+ continue;
+ total_gb_size_per_controller += 1 << (
+ ((regs->cs[i].config >> 14) & 0x3) + 2 +
+ ((regs->cs[i].config >> 8) & 0x7) + 12 +
+ ((regs->cs[i].config >> 4) & 0x3) + 0 +
+ ((regs->cs[i].config >> 0) & 0x7) + 8 +
+ 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
+ 26); /* minus 26 (count of 64M) */
+ }
+ if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */
+ total_gb_size_per_controller *= 3;
+ else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
+ total_gb_size_per_controller <<= 1;
+ /*
+ * total memory / bus width = transactions needed
+ * transactions needed / data rate = seconds
+ * to add plenty of buffer, double the time
+ * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
+ * Let's wait for 800ms
+ */
+ bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+ >> SDRAM_CFG_DBW_SHIFT);
+ timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
+ (get_ddr_freq(0) >> 20)) << 2;
+ total_gb_size_per_controller >>= 4; /* shift down to gb size */
+ debug("total %d GB\n", total_gb_size_per_controller);
+ debug("Need to wait up to %d * 10ms\n", timeout);
+
+ /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
+ while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
+ (timeout >= 0)) {
+ udelay(10000); /* throttle polling rate */
+ timeout--;
+ }
+
+ if (timeout <= 0)
+ printf("Waiting for D_INIT timeout. Memory may not work.\n");
+
+}
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index ebf3ed6..cfe1e1f 100644
--- a/drivers/ddr/fsl/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * Copyright 2010-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -153,25 +153,38 @@ static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
static const struct options_string options[] = {
COMMON_TIMING(tckmin_x_ps),
COMMON_TIMING(tckmax_ps),
- COMMON_TIMING(tckmax_max_ps),
+ COMMON_TIMING(taamin_ps),
COMMON_TIMING(trcd_ps),
COMMON_TIMING(trp_ps),
COMMON_TIMING(tras_ps),
- COMMON_TIMING(twr_ps),
+
+#ifdef CONFIG_SYS_FSL_DDR4
+ COMMON_TIMING(trfc1_ps),
+ COMMON_TIMING(trfc2_ps),
+ COMMON_TIMING(trfc4_ps),
+ COMMON_TIMING(trrds_ps),
+ COMMON_TIMING(trrdl_ps),
+ COMMON_TIMING(tccdl_ps),
+#else
COMMON_TIMING(twtr_ps),
COMMON_TIMING(trfc_ps),
COMMON_TIMING(trrd_ps),
+ COMMON_TIMING(trtp_ps),
+#endif
+ COMMON_TIMING(twr_ps),
COMMON_TIMING(trc_ps),
COMMON_TIMING(refresh_rate_ps),
+ COMMON_TIMING(extended_op_srt),
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
COMMON_TIMING(tis_ps),
COMMON_TIMING(tih_ps),
COMMON_TIMING(tds_ps),
COMMON_TIMING(tdh_ps),
- COMMON_TIMING(trtp_ps),
COMMON_TIMING(tdqsq_max_ps),
COMMON_TIMING(tqhs_ps),
+#endif
COMMON_TIMING(ndimms_present),
- COMMON_TIMING(lowest_common_SPD_caslat),
+ COMMON_TIMING(lowest_common_spd_caslat),
COMMON_TIMING(highest_common_derated_caslat),
COMMON_TIMING(additive_latency),
COMMON_TIMING(all_dimms_burst_lengths_bitmask),
@@ -211,7 +224,12 @@ static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
DIMM_PARM(n_row_addr),
DIMM_PARM(n_col_addr),
DIMM_PARM(edc_config),
+#ifdef CONFIG_SYS_FSL_DDR4
+ DIMM_PARM(bank_addr_bits),
+ DIMM_PARM(bank_group_bits),
+#else
DIMM_PARM(n_banks_per_sdram_device),
+#endif
DIMM_PARM(burst_lengths_bitmask),
DIMM_PARM(row_density),
@@ -229,20 +247,32 @@ static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
DIMM_PARM(trcd_ps),
DIMM_PARM(trp_ps),
DIMM_PARM(tras_ps),
+#ifdef CONFIG_SYS_FSL_DDR4
+ DIMM_PARM(trfc1_ps),
+ DIMM_PARM(trfc2_ps),
+ DIMM_PARM(trfc4_ps),
+ DIMM_PARM(trrds_ps),
+ DIMM_PARM(trrdl_ps),
+ DIMM_PARM(tccdl_ps),
+#else
DIMM_PARM(twr_ps),
DIMM_PARM(twtr_ps),
DIMM_PARM(trfc_ps),
DIMM_PARM(trrd_ps),
+ DIMM_PARM(trtp_ps),
+#endif
DIMM_PARM(trc_ps),
DIMM_PARM(refresh_rate_ps),
+ DIMM_PARM(extended_op_srt),
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
DIMM_PARM(tis_ps),
DIMM_PARM(tih_ps),
DIMM_PARM(tds_ps),
DIMM_PARM(tdh_ps),
- DIMM_PARM(trtp_ps),
DIMM_PARM(tdqsq_max_ps),
DIMM_PARM(tqhs_ps),
+#endif
DIMM_PARM(rank_density),
DIMM_PARM(capacity),
@@ -270,7 +300,12 @@ static void print_dimm_parameters(const dimm_params_t *pdimm)
DIMM_PARM(n_row_addr),
DIMM_PARM(n_col_addr),
DIMM_PARM(edc_config),
+#ifdef CONFIG_SYS_FSL_DDR4
+ DIMM_PARM(bank_addr_bits),
+ DIMM_PARM(bank_group_bits),
+#else
DIMM_PARM(n_banks_per_sdram_device),
+#endif
DIMM_PARM(tckmin_x_ps),
DIMM_PARM(tckmin_x_minus_1_ps),
@@ -286,20 +321,31 @@ static void print_dimm_parameters(const dimm_params_t *pdimm)
DIMM_PARM(trcd_ps),
DIMM_PARM(trp_ps),
DIMM_PARM(tras_ps),
+#ifdef CONFIG_SYS_FSL_DDR4
+ DIMM_PARM(trfc1_ps),
+ DIMM_PARM(trfc2_ps),
+ DIMM_PARM(trfc4_ps),
+ DIMM_PARM(trrds_ps),
+ DIMM_PARM(trrdl_ps),
+ DIMM_PARM(tccdl_ps),
+#else
DIMM_PARM(twr_ps),
DIMM_PARM(twtr_ps),
DIMM_PARM(trfc_ps),
DIMM_PARM(trrd_ps),
+ DIMM_PARM(trtp_ps),
+#endif
DIMM_PARM(trc_ps),
DIMM_PARM(refresh_rate_ps),
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
DIMM_PARM(tis_ps),
DIMM_PARM(tih_ps),
DIMM_PARM(tds_ps),
DIMM_PARM(tdh_ps),
- DIMM_PARM(trtp_ps),
DIMM_PARM(tdqsq_max_ps),
DIMM_PARM(tqhs_ps),
+#endif
};
static const unsigned int n_opts = ARRAY_SIZE(options);
@@ -326,23 +372,36 @@ static void print_lowest_common_dimm_parameters(
const common_timing_params_t *plcd_dimm_params)
{
static const struct options_string options[] = {
- COMMON_TIMING(tckmax_max_ps),
+ COMMON_TIMING(taamin_ps),
COMMON_TIMING(trcd_ps),
COMMON_TIMING(trp_ps),
COMMON_TIMING(tras_ps),
- COMMON_TIMING(twr_ps),
+#ifdef CONFIG_SYS_FSL_DDR4
+ COMMON_TIMING(trfc1_ps),
+ COMMON_TIMING(trfc2_ps),
+ COMMON_TIMING(trfc4_ps),
+ COMMON_TIMING(trrds_ps),
+ COMMON_TIMING(trrdl_ps),
+ COMMON_TIMING(tccdl_ps),
+#else
COMMON_TIMING(twtr_ps),
COMMON_TIMING(trfc_ps),
COMMON_TIMING(trrd_ps),
+ COMMON_TIMING(trtp_ps),
+#endif
+ COMMON_TIMING(twr_ps),
COMMON_TIMING(trc_ps),
COMMON_TIMING(refresh_rate_ps),
+ COMMON_TIMING(extended_op_srt),
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
COMMON_TIMING(tis_ps),
+ COMMON_TIMING(tih_ps),
COMMON_TIMING(tds_ps),
COMMON_TIMING(tdh_ps),
- COMMON_TIMING(trtp_ps),
COMMON_TIMING(tdqsq_max_ps),
COMMON_TIMING(tqhs_ps),
- COMMON_TIMING(lowest_common_SPD_caslat),
+#endif
+ COMMON_TIMING(lowest_common_spd_caslat),
COMMON_TIMING(highest_common_derated_caslat),
COMMON_TIMING(additive_latency),
COMMON_TIMING(ndimms_present),
@@ -460,6 +519,9 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
CTRL_OPTIONS(tfaw_window_four_activates_ps),
CTRL_OPTIONS(trwt_override),
CTRL_OPTIONS(trwt),
+ CTRL_OPTIONS(rtt_override),
+ CTRL_OPTIONS(rtt_override_value),
+ CTRL_OPTIONS(rtt_wr_override_value),
};
static const unsigned int n_opts = ARRAY_SIZE(options);
@@ -505,6 +567,7 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
CFG_REGS(timing_cfg_2),
CFG_REGS(ddr_sdram_cfg),
CFG_REGS(ddr_sdram_cfg_2),
+ CFG_REGS(ddr_sdram_cfg_3),
CFG_REGS(ddr_sdram_mode),
CFG_REGS(ddr_sdram_mode_2),
CFG_REGS(ddr_sdram_mode_3),
@@ -513,6 +576,16 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
CFG_REGS(ddr_sdram_mode_6),
CFG_REGS(ddr_sdram_mode_7),
CFG_REGS(ddr_sdram_mode_8),
+#ifdef CONFIG_SYS_FSL_DDR4
+ CFG_REGS(ddr_sdram_mode_9),
+ CFG_REGS(ddr_sdram_mode_10),
+ CFG_REGS(ddr_sdram_mode_11),
+ CFG_REGS(ddr_sdram_mode_12),
+ CFG_REGS(ddr_sdram_mode_13),
+ CFG_REGS(ddr_sdram_mode_14),
+ CFG_REGS(ddr_sdram_mode_15),
+ CFG_REGS(ddr_sdram_mode_16),
+#endif
CFG_REGS(ddr_sdram_interval),
CFG_REGS(ddr_data_init),
CFG_REGS(ddr_sdram_clk_cntl),
@@ -520,6 +593,12 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
CFG_REGS(ddr_init_ext_addr),
CFG_REGS(timing_cfg_4),
CFG_REGS(timing_cfg_5),
+#ifdef CONFIG_SYS_FSL_DDR4
+ CFG_REGS(timing_cfg_6),
+ CFG_REGS(timing_cfg_7),
+ CFG_REGS(timing_cfg_8),
+ CFG_REGS(timing_cfg_9),
+#endif
CFG_REGS(ddr_zq_cntl),
CFG_REGS(ddr_wrlvl_cntl),
CFG_REGS(ddr_wrlvl_cntl_2),
@@ -529,6 +608,10 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
CFG_REGS(ddr_sdram_rcw_2),
CFG_REGS(ddr_cdr1),
CFG_REGS(ddr_cdr2),
+ CFG_REGS(dq_map_0),
+ CFG_REGS(dq_map_1),
+ CFG_REGS(dq_map_2),
+ CFG_REGS(dq_map_3),
CFG_REGS(err_disable),
CFG_REGS(err_int_en),
CFG_REGS(ddr_eor),
@@ -574,6 +657,7 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
CFG_REGS(timing_cfg_2),
CFG_REGS(ddr_sdram_cfg),
CFG_REGS(ddr_sdram_cfg_2),
+ CFG_REGS(ddr_sdram_cfg_3),
CFG_REGS(ddr_sdram_mode),
CFG_REGS(ddr_sdram_mode_2),
CFG_REGS(ddr_sdram_mode_3),
@@ -582,6 +666,16 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
CFG_REGS(ddr_sdram_mode_6),
CFG_REGS(ddr_sdram_mode_7),
CFG_REGS(ddr_sdram_mode_8),
+#ifdef CONFIG_SYS_FSL_DDR4
+ CFG_REGS(ddr_sdram_mode_9),
+ CFG_REGS(ddr_sdram_mode_10),
+ CFG_REGS(ddr_sdram_mode_11),
+ CFG_REGS(ddr_sdram_mode_12),
+ CFG_REGS(ddr_sdram_mode_13),
+ CFG_REGS(ddr_sdram_mode_14),
+ CFG_REGS(ddr_sdram_mode_15),
+ CFG_REGS(ddr_sdram_mode_16),
+#endif
CFG_REGS(ddr_sdram_interval),
CFG_REGS(ddr_data_init),
CFG_REGS(ddr_sdram_clk_cntl),
@@ -589,6 +683,12 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
CFG_REGS(ddr_init_ext_addr),
CFG_REGS(timing_cfg_4),
CFG_REGS(timing_cfg_5),
+#ifdef CONFIG_SYS_FSL_DDR4
+ CFG_REGS(timing_cfg_6),
+ CFG_REGS(timing_cfg_7),
+ CFG_REGS(timing_cfg_8),
+ CFG_REGS(timing_cfg_9),
+#endif
CFG_REGS(ddr_zq_cntl),
CFG_REGS(ddr_wrlvl_cntl),
CFG_REGS(ddr_wrlvl_cntl_2),
@@ -598,6 +698,10 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
CFG_REGS(ddr_sdram_rcw_2),
CFG_REGS(ddr_cdr1),
CFG_REGS(ddr_cdr2),
+ CFG_REGS(dq_map_0),
+ CFG_REGS(dq_map_1),
+ CFG_REGS(dq_map_2),
+ CFG_REGS(dq_map_3),
CFG_REGS(err_disable),
CFG_REGS(err_int_en),
CFG_REGS(ddr_sdram_rcw_2),
@@ -705,6 +809,9 @@ static void print_memctl_options(const memctl_options_t *popts)
CTRL_OPTIONS(tfaw_window_four_activates_ps),
CTRL_OPTIONS(trwt_override),
CTRL_OPTIONS(trwt),
+ CTRL_OPTIONS(rtt_override),
+ CTRL_OPTIONS(rtt_override_value),
+ CTRL_OPTIONS(rtt_wr_override_value),
};
static const unsigned int n_opts = ARRAY_SIZE(options);
@@ -1245,6 +1352,266 @@ void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
}
#endif
+#ifdef CONFIG_SYS_FSL_DDR4
+void ddr4_spd_dump(const struct ddr4_spd_eeprom_s *spd)
+{
+ unsigned int i;
+
+ /* General Section: Bytes 0-127 */
+
+#define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y);
+#define PRINT_NNXXS(n0, n1, x0, x1, s) \
+ printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
+
+ PRINT_NXS(0, spd->info_size_crc,
+ "info_size_crc bytes written into serial memory, CRC coverage");
+ PRINT_NXS(1, spd->spd_rev,
+ "spd_rev SPD Revision");
+ PRINT_NXS(2, spd->mem_type,
+ "mem_type Key Byte / DRAM Device Type");
+ PRINT_NXS(3, spd->module_type,
+ "module_type Key Byte / Module Type");
+ PRINT_NXS(4, spd->density_banks,
+ "density_banks SDRAM Density and Banks");
+ PRINT_NXS(5, spd->addressing,
+ "addressing SDRAM Addressing");
+ PRINT_NXS(6, spd->package_type,
+ "package_type Package type");
+ PRINT_NXS(7, spd->opt_feature,
+ "opt_feature Optional features");
+ PRINT_NXS(8, spd->thermal_ref,
+ "thermal_ref Thermal and Refresh options");
+ PRINT_NXS(9, spd->oth_opt_features,
+ "oth_opt_features Other SDRAM optional features");
+ PRINT_NXS(10, spd->res_10,
+ "res_10 Reserved");
+ PRINT_NXS(11, spd->module_vdd,
+ "module_vdd Module Nominal Voltage, VDD");
+ PRINT_NXS(12, spd->organization,
+ "organization Module Organization");
+ PRINT_NXS(13, spd->bus_width,
+ "bus_width Module Memory Bus Width");
+ PRINT_NXS(14, spd->therm_sensor,
+ "therm_sensor Module Thermal Sensor");
+ PRINT_NXS(15, spd->ext_type,
+ "ext_type Extended module type");
+ PRINT_NXS(16, spd->res_16,
+ "res_16 Reserved");
+ PRINT_NXS(17, spd->timebases,
+ "timebases MTb and FTB");
+ PRINT_NXS(18, spd->tck_min,
+ "tck_min tCKAVGmin");
+ PRINT_NXS(19, spd->tck_max,
+ "tck_max TCKAVGmax");
+ PRINT_NXS(20, spd->caslat_b1,
+ "caslat_b1 CAS latencies, 1st byte");
+ PRINT_NXS(21, spd->caslat_b2,
+ "caslat_b2 CAS latencies, 2nd byte");
+ PRINT_NXS(22, spd->caslat_b3,
+ "caslat_b3 CAS latencies, 3rd byte ");
+ PRINT_NXS(23, spd->caslat_b4,
+ "caslat_b4 CAS latencies, 4th byte");
+ PRINT_NXS(24, spd->taa_min,
+ "taa_min Min CAS Latency Time");
+ PRINT_NXS(25, spd->trcd_min,
+ "trcd_min Min RAS# to CAS# Delay Time");
+ PRINT_NXS(26, spd->trp_min,
+ "trp_min Min Row Precharge Delay Time");
+ PRINT_NXS(27, spd->tras_trc_ext,
+ "tras_trc_ext Upper Nibbles for tRAS and tRC");
+ PRINT_NXS(28, spd->tras_min_lsb,
+ "tras_min_lsb tRASmin, lsb");
+ PRINT_NXS(29, spd->trc_min_lsb,
+ "trc_min_lsb tRCmin, lsb");
+ PRINT_NXS(30, spd->trfc1_min_lsb,
+ "trfc1_min_lsb Min Refresh Recovery Delay Time, LSB");
+ PRINT_NXS(31, spd->trfc1_min_msb,
+ "trfc1_min_msb Min Refresh Recovery Delay Time, MSB ");
+ PRINT_NXS(32, spd->trfc2_min_lsb,
+ "trfc2_min_lsb Min Refresh Recovery Delay Time, LSB");
+ PRINT_NXS(33, spd->trfc2_min_msb,
+ "trfc2_min_msb Min Refresh Recovery Delay Time, MSB");
+ PRINT_NXS(34, spd->trfc4_min_lsb,
+ "trfc4_min_lsb Min Refresh Recovery Delay Time, LSB");
+ PRINT_NXS(35, spd->trfc4_min_msb,
+ "trfc4_min_msb Min Refresh Recovery Delay Time, MSB");
+ PRINT_NXS(36, spd->tfaw_msb,
+ "tfaw_msb Upper Nibble for tFAW");
+ PRINT_NXS(37, spd->tfaw_min,
+ "tfaw_min tFAW, lsb");
+ PRINT_NXS(38, spd->trrds_min,
+ "trrds_min tRRD_Smin, MTB");
+ PRINT_NXS(39, spd->trrdl_min,
+ "trrdl_min tRRD_Lmin, MTB");
+ PRINT_NXS(40, spd->tccdl_min,
+ "tccdl_min tCCS_Lmin, MTB");
+
+ printf("%-3d-%3d: ", 41, 59); /* Reserved, General Section */
+ for (i = 41; i <= 59; i++)
+ printf("%02x ", spd->res_41[i - 41]);
+
+ puts("\n");
+ printf("%-3d-%3d: ", 60, 77);
+ for (i = 60; i <= 77; i++)
+ printf("%02x ", spd->mapping[i - 60]);
+ puts(" mapping[] Connector to SDRAM bit map\n");
+
+ PRINT_NXS(117, spd->fine_tccdl_min,
+ "fine_tccdl_min Fine offset for tCCD_Lmin");
+ PRINT_NXS(118, spd->fine_trrdl_min,
+ "fine_trrdl_min Fine offset for tRRD_Lmin");
+ PRINT_NXS(119, spd->fine_trrds_min,
+ "fine_trrds_min Fine offset for tRRD_Smin");
+ PRINT_NXS(120, spd->fine_trc_min,
+ "fine_trc_min Fine offset for tRCmin");
+ PRINT_NXS(121, spd->fine_trp_min,
+ "fine_trp_min Fine offset for tRPmin");
+ PRINT_NXS(122, spd->fine_trcd_min,
+ "fine_trcd_min Fine offset for tRCDmin");
+ PRINT_NXS(123, spd->fine_taa_min,
+ "fine_taa_min Fine offset for tAAmin");
+ PRINT_NXS(124, spd->fine_tck_max,
+ "fine_tck_max Fine offset for tCKAVGmax");
+ PRINT_NXS(125, spd->fine_tck_min,
+ "fine_tck_min Fine offset for tCKAVGmin");
+
+ /* CRC: Bytes 126-127 */
+ PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC");
+
+ switch (spd->module_type) {
+ case 0x02: /* UDIMM */
+ case 0x03: /* SO-DIMM */
+ PRINT_NXS(128, spd->mod_section.unbuffered.mod_height,
+ "mod_height (Unbuffered) Module Nominal Height");
+ PRINT_NXS(129, spd->mod_section.unbuffered.mod_thickness,
+ "mod_thickness (Unbuffered) Module Maximum Thickness");
+ PRINT_NXS(130, spd->mod_section.unbuffered.ref_raw_card,
+ "ref_raw_card (Unbuffered) Reference Raw Card Used");
+ PRINT_NXS(131, spd->mod_section.unbuffered.addr_mapping,
+ "addr_mapping (Unbuffered) Address mapping from Edge Connector to DRAM");
+ PRINT_NNXXS(254, 255, spd->mod_section.unbuffered.crc[0],
+ spd->mod_section.unbuffered.crc[1], " Module CRC");
+ break;
+ case 0x01: /* RDIMM */
+ PRINT_NXS(128, spd->mod_section.registered.mod_height,
+ "mod_height (Registered) Module Nominal Height");
+ PRINT_NXS(129, spd->mod_section.registered.mod_thickness,
+ "mod_thickness (Registered) Module Maximum Thickness");
+ PRINT_NXS(130, spd->mod_section.registered.ref_raw_card,
+ "ref_raw_card (Registered) Reference Raw Card Used");
+ PRINT_NXS(131, spd->mod_section.registered.modu_attr,
+ "modu_attr (Registered) DIMM Module Attributes");
+ PRINT_NXS(132, spd->mod_section.registered.thermal,
+ "thermal (Registered) Thermal Heat Spreader Solution");
+ PRINT_NXS(133, spd->mod_section.registered.reg_id_lo,
+ "reg_id_lo (Registered) Register Manufacturer ID Code, LSB");
+ PRINT_NXS(134, spd->mod_section.registered.reg_id_hi,
+ "reg_id_hi (Registered) Register Manufacturer ID Code, MSB");
+ PRINT_NXS(135, spd->mod_section.registered.reg_rev,
+ "reg_rev (Registered) Register Revision Number");
+ PRINT_NXS(136, spd->mod_section.registered.reg_map,
+ "reg_map (Registered) Address mapping");
+ PRINT_NNXXS(254, 255, spd->mod_section.registered.crc[0],
+ spd->mod_section.registered.crc[1], " Module CRC");
+ break;
+ case 0x04: /* LRDIMM */
+ PRINT_NXS(128, spd->mod_section.loadreduced.mod_height,
+ "mod_height (Loadreduced) Module Nominal Height");
+ PRINT_NXS(129, spd->mod_section.loadreduced.mod_thickness,
+ "mod_thickness (Loadreduced) Module Maximum Thickness");
+ PRINT_NXS(130, spd->mod_section.loadreduced.ref_raw_card,
+ "ref_raw_card (Loadreduced) Reference Raw Card Used");
+ PRINT_NXS(131, spd->mod_section.loadreduced.modu_attr,
+ "modu_attr (Loadreduced) DIMM Module Attributes");
+ PRINT_NXS(132, spd->mod_section.loadreduced.thermal,
+ "thermal (Loadreduced) Thermal Heat Spreader Solution");
+ PRINT_NXS(133, spd->mod_section.loadreduced.reg_id_lo,
+ "reg_id_lo (Loadreduced) Register Manufacturer ID Code, LSB");
+ PRINT_NXS(134, spd->mod_section.loadreduced.reg_id_hi,
+ "reg_id_hi (Loadreduced) Register Manufacturer ID Code, MSB");
+ PRINT_NXS(135, spd->mod_section.loadreduced.reg_rev,
+ "reg_rev (Loadreduced) Register Revision Number");
+ PRINT_NXS(136, spd->mod_section.loadreduced.reg_map,
+ "reg_map (Loadreduced) Address mapping");
+ PRINT_NXS(137, spd->mod_section.loadreduced.reg_drv,
+ "reg_drv (Loadreduced) Reg output drive strength");
+ PRINT_NXS(138, spd->mod_section.loadreduced.reg_drv_ck,
+ "reg_drv_ck (Loadreduced) Reg output drive strength for CK");
+ PRINT_NXS(139, spd->mod_section.loadreduced.data_buf_rev,
+ "data_buf_rev (Loadreduced) Data Buffer Revision Numbe");
+ PRINT_NXS(140, spd->mod_section.loadreduced.vrefqe_r0,
+ "vrefqe_r0 (Loadreduced) DRAM VrefDQ for Package Rank 0");
+ PRINT_NXS(141, spd->mod_section.loadreduced.vrefqe_r1,
+ "vrefqe_r1 (Loadreduced) DRAM VrefDQ for Package Rank 1");
+ PRINT_NXS(142, spd->mod_section.loadreduced.vrefqe_r2,
+ "vrefqe_r2 (Loadreduced) DRAM VrefDQ for Package Rank 2");
+ PRINT_NXS(143, spd->mod_section.loadreduced.vrefqe_r3,
+ "vrefqe_r3 (Loadreduced) DRAM VrefDQ for Package Rank 3");
+ PRINT_NXS(144, spd->mod_section.loadreduced.data_intf,
+ "data_intf (Loadreduced) Data Buffer VrefDQ for DRAM Interface");
+ PRINT_NXS(145, spd->mod_section.loadreduced.data_drv_1866,
+ "data_drv_1866 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
+ PRINT_NXS(146, spd->mod_section.loadreduced.data_drv_2400,
+ "data_drv_2400 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
+ PRINT_NXS(147, spd->mod_section.loadreduced.data_drv_3200,
+ "data_drv_3200 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
+ PRINT_NXS(148, spd->mod_section.loadreduced.dram_drv,
+ "dram_drv (Loadreduced) DRAM Drive Strength");
+ PRINT_NXS(149, spd->mod_section.loadreduced.dram_odt_1866,
+ "dram_odt_1866 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
+ PRINT_NXS(150, spd->mod_section.loadreduced.dram_odt_2400,
+ "dram_odt_2400 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
+ PRINT_NXS(151, spd->mod_section.loadreduced.dram_odt_3200,
+ "dram_odt_3200 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
+ PRINT_NXS(152, spd->mod_section.loadreduced.dram_odt_park_1866,
+ "dram_odt_park_1866 (Loadreduced) DRAM ODT (RTT_PARK)");
+ PRINT_NXS(153, spd->mod_section.loadreduced.dram_odt_park_2400,
+ "dram_odt_park_2400 (Loadreduced) DRAM ODT (RTT_PARK)");
+ PRINT_NXS(154, spd->mod_section.loadreduced.dram_odt_park_3200,
+ "dram_odt_park_3200 (Loadreduced) DRAM ODT (RTT_PARK)");
+ PRINT_NNXXS(254, 255, spd->mod_section.loadreduced.crc[0],
+ spd->mod_section.loadreduced.crc[1],
+ " Module CRC");
+ break;
+ default:
+ /* Module-specific Section, Unsupported Module Type */
+ printf("%-3d-%3d: ", 128, 255);
+
+ for (i = 128; i <= 255; i++)
+ printf("%02x", spd->mod_section.uc[i - 60]);
+
+ break;
+ }
+
+ /* Unique Module ID: Bytes 320-383 */
+ PRINT_NXS(320, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
+ PRINT_NXS(321, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
+ PRINT_NXS(322, spd->mloc, "Mfg Location");
+ PRINT_NNXXS(323, 324, spd->mdate[0], spd->mdate[1], "Mfg Date");
+
+ printf("%-3d-%3d: ", 325, 328);
+
+ for (i = 325; i <= 328; i++)
+ printf("%02x ", spd->sernum[i - 325]);
+ printf(" Module Serial Number\n");
+
+ printf("%-3d-%3d: ", 329, 348);
+ for (i = 329; i <= 348; i++)
+ printf("%02x ", spd->mpart[i - 329]);
+ printf(" Mfg's Module Part Number\n");
+
+ PRINT_NXS(349, spd->mrev, "Module Revision code");
+ PRINT_NXS(350, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
+ PRINT_NXS(351, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
+ PRINT_NXS(352, spd->stepping, "DRAM stepping");
+
+ printf("%-3d-%3d: ", 353, 381);
+ for (i = 353; i <= 381; i++)
+ printf("%02x ", spd->msd[i - 353]);
+ printf(" Mfg's Specific Data\n");
+}
+#endif
+
static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
{
#if defined(CONFIG_SYS_FSL_DDR1)
@@ -1253,6 +1620,8 @@ static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
ddr2_spd_dump(spd);
#elif defined(CONFIG_SYS_FSL_DDR3)
ddr3_spd_dump(spd);
+#elif defined(CONFIG_SYS_FSL_DDR4)
+ ddr4_spd_dump(spd);
#endif
}
diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c
index 610318a..05a24dd 100644
--- a/drivers/ddr/fsl/lc_common_dimm_params.c
+++ b/drivers/ddr/fsl/lc_common_dimm_params.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -11,20 +11,23 @@
#include <fsl_ddr.h>
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
static unsigned int
-compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
- common_timing_params_t *outpdimm,
- unsigned int number_of_dimms)
+compute_cas_latency(const dimm_params_t *dimm_params,
+ common_timing_params_t *outpdimm,
+ unsigned int number_of_dimms)
{
unsigned int i;
- unsigned int taamin_ps = 0;
- unsigned int tckmin_x_ps = 0;
unsigned int common_caslat;
unsigned int caslat_actual;
unsigned int retry = 16;
unsigned int tmp;
const unsigned int mclk_ps = get_memory_clk_period_ps();
+#ifdef CONFIG_SYS_FSL_DDR3
+ const unsigned int taamax = 20000;
+#else
+ const unsigned int taamax = 18000;
+#endif
/* compute the common CAS latency supported between slots */
tmp = dimm_params[0].caslat_x;
@@ -34,19 +37,20 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
}
common_caslat = tmp;
- /* compute the max tAAmin tCKmin between slots */
- for (i = 0; i < number_of_dimms; i++) {
- taamin_ps = max(taamin_ps, dimm_params[i].taa_ps);
- tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps);
- }
/* validate if the memory clk is in the range of dimms */
- if (mclk_ps < tckmin_x_ps) {
+ if (mclk_ps < outpdimm->tckmin_x_ps) {
printf("DDR clock (MCLK cycle %u ps) is faster than "
"the slowest DIMM(s) (tCKmin %u ps) can support.\n",
- mclk_ps, tckmin_x_ps);
+ mclk_ps, outpdimm->tckmin_x_ps);
+ }
+#ifdef CONFIG_SYS_FSL_DDR4
+ if (mclk_ps > outpdimm->tckmax_ps) {
+ printf("DDR clock (MCLK cycle %u ps) is slower than DIMM(s) (tCKmax %u ps) can support.\n",
+ mclk_ps, outpdimm->tckmax_ps);
}
+#endif
/* determine the acutal cas latency */
- caslat_actual = (taamin_ps + mclk_ps - 1) / mclk_ps;
+ caslat_actual = (outpdimm->taamin_ps + mclk_ps - 1) / mclk_ps;
/* check if the dimms support the CAS latency */
while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
caslat_actual++;
@@ -54,13 +58,147 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
}
/* once the caculation of caslat_actual is completed
* we must verify that this CAS latency value does not
- * exceed tAAmax, which is 20 ns for all DDR3 speed grades
+ * exceed tAAmax, which is 20 ns for all DDR3 speed grades,
+ * 18ns for all DDR4 speed grades.
*/
- if (caslat_actual * mclk_ps > 20000) {
+ if (caslat_actual * mclk_ps > taamax) {
printf("The choosen cas latency %d is too large\n",
caslat_actual);
}
- outpdimm->lowest_common_SPD_caslat = caslat_actual;
+ outpdimm->lowest_common_spd_caslat = caslat_actual;
+ debug("lowest_common_spd_caslat is 0x%x\n", caslat_actual);
+
+ return 0;
+}
+#else /* for DDR1 and DDR2 */
+static unsigned int
+compute_cas_latency(const dimm_params_t *dimm_params,
+ common_timing_params_t *outpdimm,
+ unsigned int number_of_dimms)
+{
+ int i;
+ const unsigned int mclk_ps = get_memory_clk_period_ps();
+ unsigned int lowest_good_caslat;
+ unsigned int not_ok;
+ unsigned int temp1, temp2;
+
+ debug("using mclk_ps = %u\n", mclk_ps);
+ if (mclk_ps > outpdimm->tckmax_ps) {
+ printf("Warning: DDR clock (%u ps) is slower than DIMM(s) (tCKmax %u ps)\n",
+ mclk_ps, outpdimm->tckmax_ps);
+ }
+
+ /*
+ * Compute a CAS latency suitable for all DIMMs
+ *
+ * Strategy for SPD-defined latencies: compute only
+ * CAS latency defined by all DIMMs.
+ */
+
+ /*
+ * Step 1: find CAS latency common to all DIMMs using bitwise
+ * operation.
+ */
+ temp1 = 0xFF;
+ for (i = 0; i < number_of_dimms; i++) {
+ if (dimm_params[i].n_ranks) {
+ temp2 = 0;
+ temp2 |= 1 << dimm_params[i].caslat_x;
+ temp2 |= 1 << dimm_params[i].caslat_x_minus_1;
+ temp2 |= 1 << dimm_params[i].caslat_x_minus_2;
+ /*
+ * If there was no entry for X-2 (X-1) in
+ * the SPD, then caslat_x_minus_2
+ * (caslat_x_minus_1) contains either 255 or
+ * 0xFFFFFFFF because that's what the glorious
+ * __ilog2 function returns for an input of 0.
+ * On 32-bit PowerPC, left shift counts with bit
+ * 26 set (that the value of 255 or 0xFFFFFFFF
+ * will have), cause the destination register to
+ * be 0. That is why this works.
+ */
+ temp1 &= temp2;
+ }
+ }
+
+ /*
+ * Step 2: check each common CAS latency against tCK of each
+ * DIMM's SPD.
+ */
+ lowest_good_caslat = 0;
+ temp2 = 0;
+ while (temp1) {
+ not_ok = 0;
+ temp2 = __ilog2(temp1);
+ debug("checking common caslat = %u\n", temp2);
+
+ /* Check if this CAS latency will work on all DIMMs at tCK. */
+ for (i = 0; i < number_of_dimms; i++) {
+ if (!dimm_params[i].n_ranks)
+ continue;
+
+ if (dimm_params[i].caslat_x == temp2) {
+ if (mclk_ps >= dimm_params[i].tckmin_x_ps) {
+ debug("CL = %u ok on DIMM %u at tCK=%u ps with tCKmin_X_ps of %u\n",
+ temp2, i, mclk_ps,
+ dimm_params[i].tckmin_x_ps);
+ continue;
+ } else {
+ not_ok++;
+ }
+ }
+
+ if (dimm_params[i].caslat_x_minus_1 == temp2) {
+ unsigned int tckmin_x_minus_1_ps
+ = dimm_params[i].tckmin_x_minus_1_ps;
+ if (mclk_ps >= tckmin_x_minus_1_ps) {
+ debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_1_ps of %u\n",
+ temp2, i, mclk_ps,
+ tckmin_x_minus_1_ps);
+ continue;
+ } else {
+ not_ok++;
+ }
+ }
+
+ if (dimm_params[i].caslat_x_minus_2 == temp2) {
+ unsigned int tckmin_x_minus_2_ps
+ = dimm_params[i].tckmin_x_minus_2_ps;
+ if (mclk_ps >= tckmin_x_minus_2_ps) {
+ debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_2_ps of %u\n",
+ temp2, i, mclk_ps,
+ tckmin_x_minus_2_ps);
+ continue;
+ } else {
+ not_ok++;
+ }
+ }
+ }
+
+ if (!not_ok)
+ lowest_good_caslat = temp2;
+
+ temp1 &= ~(1 << temp2);
+ }
+
+ debug("lowest common SPD-defined CAS latency = %u\n",
+ lowest_good_caslat);
+ outpdimm->lowest_common_spd_caslat = lowest_good_caslat;
+
+
+ /*
+ * Compute a common 'de-rated' CAS latency.
+ *
+ * The strategy here is to find the *highest* dereated cas latency
+ * with the assumption that all of the DIMMs will support a dereated
+ * CAS latency higher than or equal to their lowest dereated value.
+ */
+ temp1 = 0;
+ for (i = 0; i < number_of_dimms; i++)
+ temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
+
+ outpdimm->highest_common_derated_caslat = temp1;
+ debug("highest common dereated CAS latency = %u\n", temp1);
return 0;
}
@@ -82,34 +220,40 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
unsigned int tckmin_x_ps = 0;
unsigned int tckmax_ps = 0xFFFFFFFF;
- unsigned int tckmax_max_ps = 0;
unsigned int trcd_ps = 0;
unsigned int trp_ps = 0;
unsigned int tras_ps = 0;
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
+ unsigned int taamin_ps = 0;
+#endif
+#ifdef CONFIG_SYS_FSL_DDR4
+ unsigned int twr_ps = 15000;
+ unsigned int trfc1_ps = 0;
+ unsigned int trfc2_ps = 0;
+ unsigned int trfc4_ps = 0;
+ unsigned int trrds_ps = 0;
+ unsigned int trrdl_ps = 0;
+ unsigned int tccdl_ps = 0;
+#else
unsigned int twr_ps = 0;
unsigned int twtr_ps = 0;
unsigned int trfc_ps = 0;
unsigned int trrd_ps = 0;
+ unsigned int trtp_ps = 0;
+#endif
unsigned int trc_ps = 0;
unsigned int refresh_rate_ps = 0;
unsigned int extended_op_srt = 1;
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
unsigned int tis_ps = 0;
unsigned int tih_ps = 0;
unsigned int tds_ps = 0;
unsigned int tdh_ps = 0;
- unsigned int trtp_ps = 0;
unsigned int tdqsq_max_ps = 0;
unsigned int tqhs_ps = 0;
-
+#endif
unsigned int temp1, temp2;
unsigned int additive_latency = 0;
-#if !defined(CONFIG_SYS_FSL_DDR3)
- const unsigned int mclk_ps = get_memory_clk_period_ps();
- unsigned int lowest_good_caslat;
- unsigned int not_ok;
-
- debug("using mclk_ps = %u\n", mclk_ps);
-#endif
temp1 = 0;
for (i = 0; i < number_of_dimms; i++) {
@@ -146,31 +290,34 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
* i.e., this is the slowest the whole system can go.
*/
tckmax_ps = min(tckmax_ps, dimm_params[i].tckmax_ps);
-
- /* Either find maximum value to determine slowest
- * speed, delay, time, period, etc */
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
+ taamin_ps = max(taamin_ps, dimm_params[i].taa_ps);
+#endif
tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps);
- tckmax_max_ps = max(tckmax_max_ps, dimm_params[i].tckmax_ps);
trcd_ps = max(trcd_ps, dimm_params[i].trcd_ps);
trp_ps = max(trp_ps, dimm_params[i].trp_ps);
tras_ps = max(tras_ps, dimm_params[i].tras_ps);
+#ifdef CONFIG_SYS_FSL_DDR4
+ trfc1_ps = max(trfc1_ps, dimm_params[i].trfc1_ps);
+ trfc2_ps = max(trfc2_ps, dimm_params[i].trfc2_ps);
+ trfc4_ps = max(trfc4_ps, dimm_params[i].trfc4_ps);
+ trrds_ps = max(trrds_ps, dimm_params[i].trrds_ps);
+ trrdl_ps = max(trrdl_ps, dimm_params[i].trrdl_ps);
+ tccdl_ps = max(tccdl_ps, dimm_params[i].tccdl_ps);
+#else
twr_ps = max(twr_ps, dimm_params[i].twr_ps);
twtr_ps = max(twtr_ps, dimm_params[i].twtr_ps);
trfc_ps = max(trfc_ps, dimm_params[i].trfc_ps);
trrd_ps = max(trrd_ps, dimm_params[i].trrd_ps);
+ trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps);
+#endif
trc_ps = max(trc_ps, dimm_params[i].trc_ps);
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
tis_ps = max(tis_ps, dimm_params[i].tis_ps);
tih_ps = max(tih_ps, dimm_params[i].tih_ps);
tds_ps = max(tds_ps, dimm_params[i].tds_ps);
tdh_ps = max(tdh_ps, dimm_params[i].tdh_ps);
- trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps);
tqhs_ps = max(tqhs_ps, dimm_params[i].tqhs_ps);
- refresh_rate_ps = max(refresh_rate_ps,
- dimm_params[i].refresh_rate_ps);
- /* extended_op_srt is either 0 or 1, 0 having priority */
- extended_op_srt = min(extended_op_srt,
- dimm_params[i].extended_op_srt);
-
/*
* Find maximum tdqsq_max_ps to find slowest.
*
@@ -178,6 +325,12 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
* strategy for this parameter?
*/
tdqsq_max_ps = max(tdqsq_max_ps, dimm_params[i].tdqsq_max_ps);
+#endif
+ refresh_rate_ps = max(refresh_rate_ps,
+ dimm_params[i].refresh_rate_ps);
+ /* extended_op_srt is either 0 or 1, 0 having priority */
+ extended_op_srt = min(extended_op_srt,
+ dimm_params[i].extended_op_srt);
}
outpdimm->ndimms_present = number_of_dimms - temp1;
@@ -189,24 +342,37 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
outpdimm->tckmin_x_ps = tckmin_x_ps;
outpdimm->tckmax_ps = tckmax_ps;
- outpdimm->tckmax_max_ps = tckmax_max_ps;
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
+ outpdimm->taamin_ps = taamin_ps;
+#endif
outpdimm->trcd_ps = trcd_ps;
outpdimm->trp_ps = trp_ps;
outpdimm->tras_ps = tras_ps;
- outpdimm->twr_ps = twr_ps;
+#ifdef CONFIG_SYS_FSL_DDR4
+ outpdimm->trfc1_ps = trfc1_ps;
+ outpdimm->trfc2_ps = trfc2_ps;
+ outpdimm->trfc4_ps = trfc4_ps;
+ outpdimm->trrds_ps = trrds_ps;
+ outpdimm->trrdl_ps = trrdl_ps;
+ outpdimm->tccdl_ps = tccdl_ps;
+#else
outpdimm->twtr_ps = twtr_ps;
outpdimm->trfc_ps = trfc_ps;
outpdimm->trrd_ps = trrd_ps;
+ outpdimm->trtp_ps = trtp_ps;
+#endif
+ outpdimm->twr_ps = twr_ps;
outpdimm->trc_ps = trc_ps;
outpdimm->refresh_rate_ps = refresh_rate_ps;
outpdimm->extended_op_srt = extended_op_srt;
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
outpdimm->tis_ps = tis_ps;
outpdimm->tih_ps = tih_ps;
outpdimm->tds_ps = tds_ps;
outpdimm->tdh_ps = tdh_ps;
- outpdimm->trtp_ps = trtp_ps;
outpdimm->tdqsq_max_ps = tdqsq_max_ps;
outpdimm->tqhs_ps = tqhs_ps;
+#endif
/* Determine common burst length for all DIMMs. */
temp1 = 0xff;
@@ -265,128 +431,9 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
if (temp1 != 0)
printf("ERROR: Mix different RDIMM detected!\n");
-#if defined(CONFIG_SYS_FSL_DDR3)
- if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms))
+ /* calculate cas latency for all DDR types */
+ if (compute_cas_latency(dimm_params, outpdimm, number_of_dimms))
return 1;
-#else
- /*
- * Compute a CAS latency suitable for all DIMMs
- *
- * Strategy for SPD-defined latencies: compute only
- * CAS latency defined by all DIMMs.
- */
-
- /*
- * Step 1: find CAS latency common to all DIMMs using bitwise
- * operation.
- */
- temp1 = 0xFF;
- for (i = 0; i < number_of_dimms; i++) {
- if (dimm_params[i].n_ranks) {
- temp2 = 0;
- temp2 |= 1 << dimm_params[i].caslat_x;
- temp2 |= 1 << dimm_params[i].caslat_x_minus_1;
- temp2 |= 1 << dimm_params[i].caslat_x_minus_2;
- /*
- * FIXME: If there was no entry for X-2 (X-1) in
- * the SPD, then caslat_x_minus_2
- * (caslat_x_minus_1) contains either 255 or
- * 0xFFFFFFFF because that's what the glorious
- * __ilog2 function returns for an input of 0.
- * On 32-bit PowerPC, left shift counts with bit
- * 26 set (that the value of 255 or 0xFFFFFFFF
- * will have), cause the destination register to
- * be 0. That is why this works.
- */
- temp1 &= temp2;
- }
- }
-
- /*
- * Step 2: check each common CAS latency against tCK of each
- * DIMM's SPD.
- */
- lowest_good_caslat = 0;
- temp2 = 0;
- while (temp1) {
- not_ok = 0;
- temp2 = __ilog2(temp1);
- debug("checking common caslat = %u\n", temp2);
-
- /* Check if this CAS latency will work on all DIMMs at tCK. */
- for (i = 0; i < number_of_dimms; i++) {
- if (!dimm_params[i].n_ranks) {
- continue;
- }
- if (dimm_params[i].caslat_x == temp2) {
- if (mclk_ps >= dimm_params[i].tckmin_x_ps) {
- debug("CL = %u ok on DIMM %u at tCK=%u"
- " ps with its tCKmin_X_ps of %u\n",
- temp2, i, mclk_ps,
- dimm_params[i].tckmin_x_ps);
- continue;
- } else {
- not_ok++;
- }
- }
-
- if (dimm_params[i].caslat_x_minus_1 == temp2) {
- unsigned int tckmin_x_minus_1_ps
- = dimm_params[i].tckmin_x_minus_1_ps;
- if (mclk_ps >= tckmin_x_minus_1_ps) {
- debug("CL = %u ok on DIMM %u at "
- "tCK=%u ps with its "
- "tckmin_x_minus_1_ps of %u\n",
- temp2, i, mclk_ps,
- tckmin_x_minus_1_ps);
- continue;
- } else {
- not_ok++;
- }
- }
-
- if (dimm_params[i].caslat_x_minus_2 == temp2) {
- unsigned int tckmin_x_minus_2_ps
- = dimm_params[i].tckmin_x_minus_2_ps;
- if (mclk_ps >= tckmin_x_minus_2_ps) {
- debug("CL = %u ok on DIMM %u at "
- "tCK=%u ps with its "
- "tckmin_x_minus_2_ps of %u\n",
- temp2, i, mclk_ps,
- tckmin_x_minus_2_ps);
- continue;
- } else {
- not_ok++;
- }
- }
- }
-
- if (!not_ok) {
- lowest_good_caslat = temp2;
- }
-
- temp1 &= ~(1 << temp2);
- }
-
- debug("lowest common SPD-defined CAS latency = %u\n",
- lowest_good_caslat);
- outpdimm->lowest_common_SPD_caslat = lowest_good_caslat;
-
-
- /*
- * Compute a common 'de-rated' CAS latency.
- *
- * The strategy here is to find the *highest* dereated cas latency
- * with the assumption that all of the DIMMs will support a dereated
- * CAS latency higher than or equal to their lowest dereated value.
- */
- temp1 = 0;
- for (i = 0; i < number_of_dimms; i++) {
- temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
- }
- outpdimm->highest_common_derated_caslat = temp1;
- debug("highest common dereated CAS latency = %u\n", temp1);
-#endif /* #if defined(CONFIG_SYS_FSL_DDR3) */
/* Determine if all DIMMs ECC capable. */
temp1 = 1;
@@ -404,14 +451,6 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
}
outpdimm->all_dimms_ecc_capable = temp1;
-#ifndef CONFIG_SYS_FSL_DDR3
- /* FIXME: move to somewhere else to validate. */
- if (mclk_ps > tckmax_max_ps) {
- printf("Warning: some of the installed DIMMs "
- "can not operate this slowly.\n");
- return 1;
- }
-#endif
/*
* Compute additive latency.
*
@@ -468,27 +507,20 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
additive_latency = 0;
#if defined(CONFIG_SYS_FSL_DDR2)
- if (lowest_good_caslat < 4) {
- additive_latency = (picos_to_mclk(trcd_ps) > lowest_good_caslat)
- ? picos_to_mclk(trcd_ps) - lowest_good_caslat : 0;
+ if ((outpdimm->lowest_common_spd_caslat < 4) &&
+ (picos_to_mclk(trcd_ps) > outpdimm->lowest_common_spd_caslat)) {
+ additive_latency = picos_to_mclk(trcd_ps) -
+ outpdimm->lowest_common_spd_caslat;
if (mclk_to_picos(additive_latency) > trcd_ps) {
additive_latency = picos_to_mclk(trcd_ps);
debug("setting additive_latency to %u because it was "
" greater than tRCD_ps\n", additive_latency);
}
}
-
-#elif defined(CONFIG_SYS_FSL_DDR3)
- /*
- * The system will not use the global auto-precharge mode.
- * However, it uses the page mode, so we set AL=0
- */
- additive_latency = 0;
#endif
/*
* Validate additive latency
- * FIXME: move to somewhere else to validate
*
* AL <= tRCD(min)
*/
@@ -516,10 +548,19 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
debug("trcd_ps = %u\n", outpdimm->trcd_ps);
debug("trp_ps = %u\n", outpdimm->trp_ps);
debug("tras_ps = %u\n", outpdimm->tras_ps);
- debug("twr_ps = %u\n", outpdimm->twr_ps);
+#ifdef CONFIG_SYS_FSL_DDR4
+ debug("trfc1_ps = %u\n", trfc1_ps);
+ debug("trfc2_ps = %u\n", trfc2_ps);
+ debug("trfc4_ps = %u\n", trfc4_ps);
+ debug("trrds_ps = %u\n", trrds_ps);
+ debug("trrdl_ps = %u\n", trrdl_ps);
+ debug("tccdl_ps = %u\n", tccdl_ps);
+#else
debug("twtr_ps = %u\n", outpdimm->twtr_ps);
debug("trfc_ps = %u\n", outpdimm->trfc_ps);
debug("trrd_ps = %u\n", outpdimm->trrd_ps);
+#endif
+ debug("twr_ps = %u\n", outpdimm->twr_ps);
debug("trc_ps = %u\n", outpdimm->trc_ps);
return 0;
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index d62ca63..5e001fc 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -81,14 +81,37 @@ u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
#endif
+#define SPD_SPA0_ADDRESS 0x36
+#define SPD_SPA1_ADDRESS 0x37
+
static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
{
int ret;
+#ifdef CONFIG_SYS_FSL_DDR4
+ uint8_t dummy = 0;
+#endif
i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
+#ifdef CONFIG_SYS_FSL_DDR4
+ /*
+ * DDR4 SPD has 384 to 512 bytes
+ * To access the lower 256 bytes, we need to set EE page address to 0
+ * To access the upper 256 bytes, we need to set EE page address to 1
+ * See Jedec standar No. 21-C for detail
+ */
+ i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1);
+ ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256);
+ if (!ret) {
+ i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1);
+ ret = i2c_read(i2c_address, 0, 1,
+ (uchar *)((ulong)spd + 256),
+ min(256, sizeof(generic_spd_eeprom_t) - 256));
+ }
+#else
ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
sizeof(generic_spd_eeprom_t));
+#endif
if (ret) {
if (i2c_address ==
@@ -197,6 +220,11 @@ const char * step_to_string(unsigned int step) {
if ((1 << s) != step)
return step_string_tbl[7];
+ if (s >= ARRAY_SIZE(step_string_tbl)) {
+ printf("Error for the step in %s\n", __func__);
+ s = 0;
+ }
+
return step_string_tbl[s];
}
@@ -497,6 +525,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
/* STEP 5: Assign addresses to chip selects */
check_interleaving_options(pinfo);
total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
+ debug("Total mem %llu assigned\n", total_mem);
case STEP_COMPUTE_REGS:
/* STEP 6: compute controller register values */
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index c805086..4d5572e 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -15,6 +15,7 @@
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
#endif
+DECLARE_GLOBAL_DATA_PTR;
/*
* regs has the to-be-set values for DDR controller registers
@@ -43,6 +44,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
u32 save1, save2;
#endif
+#ifdef CONFIG_DEEP_SLEEP
+ const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ bool sleep_flag = 0;
+#endif
+
+#ifdef CONFIG_DEEP_SLEEP
+ if (in_be32(&gur->scrtsr[0]) & (1 << 3))
+ sleep_flag = 1;
+#endif
+
switch (ctrl_num) {
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
@@ -119,7 +130,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
- out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+#ifdef CONFIG_DEEP_SLEEP
+ if (sleep_flag)
+ out_be32(&ddr->sdram_cfg_2,
+ regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
+ else
+#endif
+ out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
@@ -132,8 +149,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
- out_be32(&ddr->init_addr, regs->ddr_init_addr);
- out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+#ifdef CONFIG_DEEP_SLEEP
+ if (sleep_flag) {
+ out_be32(&ddr->init_addr, 0);
+ out_be32(&ddr->init_ext_addr, (1 << 31));
+ } else
+#endif
+ {
+ out_be32(&ddr->init_addr, regs->ddr_init_addr);
+ out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+ }
out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
@@ -374,8 +399,22 @@ step2:
udelay(500);
asm volatile("sync;isync");
+#ifdef CONFIG_DEEP_SLEEP
+ if (sleep_flag) {
+ /* enter self-refresh */
+ setbits_be32(&ddr->sdram_cfg_2, (1 << 31));
+ /* do board specific memory setup */
+ board_mem_sleep_setup();
+ }
+#endif
+
/* Let the controller go */
- temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
+#ifdef CONFIG_DEEP_SLEEP
+ if (sleep_flag)
+ temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
+ else
+#endif
+ temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI);
out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
asm volatile("sync;isync");
@@ -526,4 +565,9 @@ step2:
clrbits_be32(&ddr->sdram_cfg, 0x2);
}
#endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
+#ifdef CONFIG_DEEP_SLEEP
+ if (sleep_flag)
+ /* exit self-refresh */
+ clrbits_be32(&ddr->sdram_cfg_2, (1 << 31));
+#endif
}
diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index b0cf046..5986e1a 100644
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008, 2010-2012 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2010-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -29,7 +29,7 @@ struct dynamic_odt {
unsigned int odt_rtt_wr;
};
-#ifdef CONFIG_SYS_FSL_DDR3
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
static const struct dynamic_odt single_Q[4] = {
{ /* cs0 */
FSL_DDR_ODT_NEVER,
@@ -259,7 +259,7 @@ static const struct dynamic_odt odt_unknown[4] = {
DDR3_RTT_OFF
}
};
-#else /* CONFIG_SYS_FSL_DDR3 */
+#else /* CONFIG_SYS_FSL_DDR3 || CONFIG_SYS_FSL_DDR4 */
static const struct dynamic_odt single_Q[4] = {
{0, 0, 0, 0},
{0, 0, 0, 0},
@@ -507,7 +507,9 @@ unsigned int populate_memctl_options(int all_dimms_registered,
unsigned int i;
char buffer[HWCONFIG_BUFFER_SIZE];
char *buf = NULL;
-#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2)
+#if defined(CONFIG_SYS_FSL_DDR3) || \
+ defined(CONFIG_SYS_FSL_DDR2) || \
+ defined(CONFIG_SYS_FSL_DDR4)
const struct dynamic_odt *pdodt = odt_unknown;
#endif
ulong ddr_freq;
@@ -519,73 +521,76 @@ unsigned int populate_memctl_options(int all_dimms_registered,
if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
buf = buffer;
-#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2)
+#if defined(CONFIG_SYS_FSL_DDR3) || \
+ defined(CONFIG_SYS_FSL_DDR2) || \
+ defined(CONFIG_SYS_FSL_DDR4)
/* Chip select options. */
- if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
- switch (pdimm[0].n_ranks) {
- case 1:
- pdodt = single_S;
- break;
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+ switch (pdimm[0].n_ranks) {
+ case 1:
+ pdodt = single_S;
+ break;
+ case 2:
+ pdodt = single_D;
+ break;
+ case 4:
+ pdodt = single_Q;
+ break;
+ }
+#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+ switch (pdimm[0].n_ranks) {
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+ case 4:
+ pdodt = single_Q;
+ if (pdimm[1].n_ranks)
+ printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n");
+ break;
+#endif
+ case 2:
+ switch (pdimm[1].n_ranks) {
case 2:
- pdodt = single_D;
+ pdodt = dual_DD;
break;
- case 4:
- pdodt = single_Q;
+ case 1:
+ pdodt = dual_DS;
break;
- }
- } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
- switch (pdimm[0].n_ranks) {
-#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
- case 4:
- pdodt = single_Q;
- if (pdimm[1].n_ranks)
- printf("Error: Quad- and Dual-rank DIMMs "
- "cannot be used together\n");
+ case 0:
+ pdodt = dual_D0;
break;
-#endif
+ }
+ break;
+ case 1:
+ switch (pdimm[1].n_ranks) {
case 2:
- switch (pdimm[1].n_ranks) {
- case 2:
- pdodt = dual_DD;
- break;
- case 1:
- pdodt = dual_DS;
- break;
- case 0:
- pdodt = dual_D0;
- break;
- }
+ pdodt = dual_SD;
break;
case 1:
- switch (pdimm[1].n_ranks) {
- case 2:
- pdodt = dual_SD;
- break;
- case 1:
- pdodt = dual_SS;
- break;
- case 0:
- pdodt = dual_S0;
- break;
- }
+ pdodt = dual_SS;
break;
case 0:
- switch (pdimm[1].n_ranks) {
- case 2:
- pdodt = dual_0D;
- break;
- case 1:
- pdodt = dual_0S;
- break;
- }
+ pdodt = dual_S0;
+ break;
+ }
+ break;
+ case 0:
+ switch (pdimm[1].n_ranks) {
+ case 2:
+ pdodt = dual_0D;
+ break;
+ case 1:
+ pdodt = dual_0S;
break;
}
+ break;
}
-#endif
+#endif /* CONFIG_DIMM_SLOTS_PER_CTLR */
+#endif /* CONFIG_SYS_FSL_DDR2, 3, 4 */
/* Pick chip-select local options. */
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2)
+#if defined(CONFIG_SYS_FSL_DDR3) || \
+ defined(CONFIG_SYS_FSL_DDR2) || \
+ defined(CONFIG_SYS_FSL_DDR4)
popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
@@ -703,7 +708,7 @@ unsigned int populate_memctl_options(int all_dimms_registered,
popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
/* Choose burst length. */
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
#if defined(CONFIG_E500MC)
popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */
popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
@@ -722,7 +727,7 @@ unsigned int populate_memctl_options(int all_dimms_registered,
#endif
/* Choose ddr controller address mirror mode */
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
popts->mirrored_dimm = pdimm[0].mirrored_dimm;
#endif
@@ -766,11 +771,9 @@ unsigned int populate_memctl_options(int all_dimms_registered,
* BSTTOPRE precharge interval
*
* Set this to 0 for global auto precharge
- *
- * FIXME: Should this be configured in picoseconds?
- * Why it should be in ps: better understanding of this
- * relative to actual DRAM timing parameters such as tRAS.
- * e.g. tRAS(min) = 40 ns
+ * The value of 0x100 has been used for DDR1, DDR2, DDR3.
+ * It is not wrong. Any value should be OK. The performance depends on
+ * applications. There is no one good value for all.
*/
popts->bstopre = 0x100;
@@ -795,12 +798,12 @@ unsigned int populate_memctl_options(int all_dimms_registered,
*/
popts->tfaw_window_four_activates_ps = 37500;
-#elif defined(CONFIG_SYS_FSL_DDR3)
+#else
popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
#endif
popts->zq_en = 0;
popts->wrlvl_en = 0;
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
/*
* due to ddr3 dimm is fly-by topology
* we suggest to enable write leveling to
@@ -843,8 +846,7 @@ unsigned int populate_memctl_options(int all_dimms_registered,
popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
popts->memctl_interleaving = 1;
debug("256 Byte interleaving\n");
- goto done;
-#endif
+#else
/*
* test null first. if CONFIG_HWCONFIG is not defined
* hwconfig_arg_cmp returns non-zero
@@ -926,8 +928,9 @@ unsigned int populate_memctl_options(int all_dimms_registered,
popts->memctl_interleaving = 0;
printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
}
+#endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */
done:
-#endif
+#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
(CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
/* test null first. if CONFIG_HWCONFIG is not defined,
@@ -1102,10 +1105,11 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo)
case FSL_DDR_PAGE_INTERLEAVING:
case FSL_DDR_BANK_INTERLEAVING:
case FSL_DDR_SUPERBANK_INTERLEAVING:
- if (3 == CONFIG_NUM_DDR_CONTROLLERS)
+#if (3 == CONFIG_NUM_DDR_CONTROLLERS)
k = 2;
- else
+#else
k = CONFIG_NUM_DDR_CONTROLLERS;
+#endif
break;
case FSL_DDR_3WAY_1KB_INTERLEAVING:
case FSL_DDR_3WAY_4KB_INTERLEAVING:
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index ad53658..7a22aa3 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -23,6 +23,18 @@
#define ULL_8FS 0xFFFFFFFFULL
+u32 fsl_ddr_get_version(void)
+{
+ struct ccsr_ddr __iomem *ddr;
+ u32 ver_major_minor_errata;
+
+ ddr = (void *)_DDR_ADDR;
+ ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8;
+ ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8;
+
+ return ver_major_minor_errata;
+}
+
/*
* Round up mclk_ps to nearest 1 ps in memory controller code
* if the error is 0.5ps or more.
@@ -175,6 +187,9 @@ void board_add_ram_info(int use_default)
case SDRAM_TYPE_DDR3:
puts("3");
break;
+ case SDRAM_TYPE_DDR4:
+ puts("4");
+ break;
default:
puts("?");
break;
@@ -188,9 +203,12 @@ void board_add_ram_info(int use_default)
puts(", 64-bit");
/* Calculate CAS latency based on timing cfg values */
- cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
- if ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 1)
- cas_lat += (8 << 1);
+ cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf);
+ if (fsl_ddr_get_version() <= 0x40400)
+ cas_lat += 1;
+ else
+ cas_lat += 2;
+ cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4;
printf(", CL=%d", cas_lat >> 1);
if (cas_lat & 0x1)
puts(".5");
diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c
index 8a09aaf..51b1026 100644
--- a/drivers/dfu/dfu.c
+++ b/drivers/dfu/dfu.c
@@ -219,7 +219,7 @@ int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num)
ret = tret;
}
- return ret = 0 ? size : ret;
+ return ret;
}
static int dfu_read_buffer_fill(struct dfu_entity *dfu, void *buf, int size)
diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c
index 651cfff..5e10ea7 100644
--- a/drivers/dfu/dfu_mmc.c
+++ b/drivers/dfu/dfu_mmc.c
@@ -184,66 +184,95 @@ int dfu_read_medium_mmc(struct dfu_entity *dfu, u64 offset, void *buf,
return ret;
}
+/*
+ * @param s Parameter string containing space-separated arguments:
+ * 1st:
+ * raw (raw read/write)
+ * fat (files)
+ * ext4 (^)
+ * part (partition image)
+ * 2nd and 3rd:
+ * lba_start and lba_size, for raw write
+ * mmc_dev and mmc_part, for filesystems and part
+ */
int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s)
{
- int dev, part;
- struct mmc *mmc;
- block_dev_desc_t *blk_dev;
- disk_partition_t partinfo;
- char *st;
-
- dfu->dev_type = DFU_DEV_MMC;
- st = strsep(&s, " ");
- if (!strcmp(st, "mmc")) {
- dfu->layout = DFU_RAW_ADDR;
- dfu->data.mmc.lba_start = simple_strtoul(s, &s, 16);
- dfu->data.mmc.lba_size = simple_strtoul(++s, &s, 16);
- dfu->data.mmc.lba_blk_size = get_mmc_blk_size(dfu->dev_num);
- } else if (!strcmp(st, "fat")) {
- dfu->layout = DFU_FS_FAT;
- } else if (!strcmp(st, "ext4")) {
- dfu->layout = DFU_FS_EXT4;
- } else if (!strcmp(st, "part")) {
+ const char *entity_type;
+ size_t second_arg;
+ size_t third_arg;
- dfu->layout = DFU_RAW_ADDR;
+ struct mmc *mmc;
- dev = simple_strtoul(s, &s, 10);
- s++;
- part = simple_strtoul(s, &s, 10);
+ const char *argv[3];
+ const char **parg = argv;
- mmc = find_mmc_device(dev);
- if (mmc == NULL || mmc_init(mmc)) {
- printf("%s: could not find mmc device #%d!\n",
- __func__, dev);
+ for (; parg < argv + sizeof(argv) / sizeof(*argv); ++parg) {
+ *parg = strsep(&s, " ");
+ if (*parg == NULL) {
+ error("Invalid number of arguments.\n");
return -ENODEV;
}
+ }
+
+ entity_type = argv[0];
+ /*
+ * Base 0 means we'll accept (prefixed with 0x or 0) base 16, 8,
+ * with default 10.
+ */
+ second_arg = simple_strtoul(argv[1], NULL, 0);
+ third_arg = simple_strtoul(argv[2], NULL, 0);
- blk_dev = &mmc->block_dev;
- if (get_partition_info(blk_dev, part, &partinfo) != 0) {
- printf("%s: could not find partition #%d on mmc device #%d!\n",
- __func__, part, dev);
+ mmc = find_mmc_device(dfu->dev_num);
+ if (mmc == NULL) {
+ error("Couldn't find MMC device no. %d.\n", dfu->dev_num);
+ return -ENODEV;
+ }
+
+ if (mmc_init(mmc)) {
+ error("Couldn't init MMC device.\n");
+ return -ENODEV;
+ }
+
+ if (!strcmp(entity_type, "raw")) {
+ dfu->layout = DFU_RAW_ADDR;
+ dfu->data.mmc.lba_start = second_arg;
+ dfu->data.mmc.lba_size = third_arg;
+ dfu->data.mmc.lba_blk_size = mmc->read_bl_len;
+ } else if (!strcmp(entity_type, "part")) {
+ disk_partition_t partinfo;
+ block_dev_desc_t *blk_dev = &mmc->block_dev;
+ int mmcdev = second_arg;
+ int mmcpart = third_arg;
+
+ if (get_partition_info(blk_dev, mmcpart, &partinfo) != 0) {
+ error("Couldn't find part #%d on mmc device #%d\n",
+ mmcpart, mmcdev);
return -ENODEV;
}
- dfu->data.mmc.lba_start = partinfo.start;
- dfu->data.mmc.lba_size = partinfo.size;
- dfu->data.mmc.lba_blk_size = partinfo.blksz;
-
+ dfu->layout = DFU_RAW_ADDR;
+ dfu->data.mmc.lba_start = partinfo.start;
+ dfu->data.mmc.lba_size = partinfo.size;
+ dfu->data.mmc.lba_blk_size = partinfo.blksz;
+ } else if (!strcmp(entity_type, "fat")) {
+ dfu->layout = DFU_FS_FAT;
+ } else if (!strcmp(entity_type, "ext4")) {
+ dfu->layout = DFU_FS_EXT4;
} else {
- printf("%s: Memory layout (%s) not supported!\n", __func__, st);
+ error("Memory layout (%s) not supported!\n", entity_type);
return -ENODEV;
}
- if (dfu->layout == DFU_FS_EXT4 || dfu->layout == DFU_FS_FAT) {
- dfu->data.mmc.dev = simple_strtoul(s, &s, 10);
- dfu->data.mmc.part = simple_strtoul(++s, &s, 10);
+ /* if it's NOT a raw write */
+ if (strcmp(entity_type, "raw")) {
+ dfu->data.mmc.dev = second_arg;
+ dfu->data.mmc.part = third_arg;
}
+ dfu->dev_type = DFU_DEV_MMC;
dfu->read_medium = dfu_read_medium_mmc;
dfu->write_medium = dfu_write_medium_mmc;
dfu->flush_medium = dfu_flush_medium_mmc;
-
- /* initial state */
dfu->inited = 0;
return 0;
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 291ad94..aa159f8 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -423,18 +423,45 @@ fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,
struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
int i = -1; /* signal error */
u8 *a = (u8*)&addr;
+ int len = alen * -1;
if (i2c_wait4bus(adap) < 0)
return -1;
- if ((!length || alen > 0)
- && i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0
- && __i2c_write(adap, &a[4 - alen], alen) == alen)
- i = 0; /* No error so far */
+ /* To handle the need of I2C devices that require to write few bytes
+ * (more than 4 bytes of address as in the case of else part)
+ * of data before reading, Negative equivalent of length(bytes to write)
+ * is passed, but used the +ve part of len for writing data
+ */
+ if (alen < 0) {
+ /* Generate a START and send the Address and
+ * the Tx Bytes to the slave.
+ * "START: Address: Write bytes data[len]"
+ * IF part supports writing any number of bytes in contrast
+ * to the else part, which supports writing address offset
+ * of upto 4 bytes only.
+ * bytes that need to be written are passed in
+ * "data", which will eventually keep the data READ,
+ * after writing the len bytes out of it
+ */
+ if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0)
+ i = __i2c_write(adap, data, len);
+
+ if (i != len)
+ return -1;
- if (length &&
- i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
- i = __i2c_read(adap, data, length);
+ if (length && i2c_write_addr(adap, dev, I2C_READ_BIT, 1) != 0)
+ i = __i2c_read(adap, data, length);
+ } else {
+ if ((!length || alen > 0) &&
+ i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
+ __i2c_write(adap, &a[4 - alen], alen) == alen)
+ i = 0; /* No error so far */
+
+ if (length &&
+ i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
+ i = __i2c_read(adap, data, length);
+ }
writeb(I2C_CR_MEN, &device->cr);
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 595019b..48468d7 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -22,6 +22,8 @@
#include <i2c.h>
#include <watchdog.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#ifdef I2C_QUIRK_REG
struct mxc_i2c_regs {
uint8_t iadr;
@@ -411,12 +413,6 @@ struct sram_data {
struct i2c_parms i2c_data[3];
};
-/*
- * For SPL boot some boards need i2c before SDRAM is initialized so force
- * variables to live in SRAM
- */
-static struct sram_data __attribute__((section(".data"))) srdata;
-
static void * const i2c_bases[] = {
#if defined(CONFIG_MX25)
(void *)IMX_I2C_BASE,
@@ -445,9 +441,10 @@ void *i2c_get_base(struct i2c_adapter *adap)
static struct i2c_parms *i2c_get_parms(void *base)
{
+ struct sram_data *srdata = (void *)gd->srdata;
int i = 0;
- struct i2c_parms *p = srdata.i2c_data;
- while (i < ARRAY_SIZE(srdata.i2c_data)) {
+ struct i2c_parms *p = srdata->i2c_data;
+ while (i < ARRAY_SIZE(srdata->i2c_data)) {
if (p->base == base)
return p;
p++;
@@ -490,8 +487,9 @@ static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
void bus_i2c_init(void *base, int speed, int unused,
int (*idle_bus_fn)(void *p), void *idle_bus_data)
{
+ struct sram_data *srdata = (void *)gd->srdata;
int i = 0;
- struct i2c_parms *p = srdata.i2c_data;
+ struct i2c_parms *p = srdata->i2c_data;
if (!base)
return;
for (;;) {
@@ -505,7 +503,7 @@ void bus_i2c_init(void *base, int speed, int unused,
}
p++;
i++;
- if (i >= ARRAY_SIZE(srdata.i2c_data))
+ if (i >= ARRAY_SIZE(srdata->i2c_data))
return;
}
bus_i2c_set_bus_speed(base, speed);
diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c
index be61973..3902e9f 100644
--- a/drivers/misc/fsl_ifc.c
+++ b/drivers/misc/fsl_ifc.c
@@ -162,3 +162,10 @@ void init_early_memctl_regs(void)
set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
#endif
}
+
+void init_final_memctl_regs(void)
+{
+#ifdef CONFIG_SYS_CSPR0_FINAL
+ set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL);
+#endif
+}
diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c
index 8fc263f..b1cb4b3 100644
--- a/drivers/mmc/fsl_esdhc_spl.c
+++ b/drivers/mmc/fsl_esdhc_spl.c
@@ -19,6 +19,32 @@
#define MBRDBR_BOOT_SIG_AA 0x1ff
#define CONFIG_CFG_DATA_SECTOR 0
+
+void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst)
+{
+ uint blk_start, blk_cnt, err;
+
+ struct mmc *mmc = find_mmc_device(0);
+ if (!mmc) {
+ puts("spl: mmc device not found!!\n");
+ hang();
+ }
+
+ if (mmc_init(mmc)) {
+ puts("MMC init failed\n");
+ return;
+ }
+
+ blk_start = ALIGN(offs, mmc->read_bl_len) / mmc->read_bl_len;
+ blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
+
+ err = mmc->block_dev.block_read(0, blk_start, blk_cnt, vdst);
+ if (err != blk_cnt) {
+ puts("spl: mmc read failed!!\n");
+ hang();
+ }
+}
+
/*
* The main entry for mmc booting. It's necessary that SDRAM is already
* configured and available since this code loads the main U-Boot image
@@ -29,10 +55,12 @@ void __noreturn mmc_boot(void)
{
__attribute__((noreturn)) void (*uboot)(void);
uint blk_start, blk_cnt, err;
- u32 blklen;
+#ifndef CONFIG_FSL_CORENET
uchar *tmp_buf;
+ u32 blklen;
uchar val;
uint i, byte_num;
+#endif
u32 offset, code_len;
struct mmc *mmc;
@@ -102,7 +130,9 @@ void __noreturn mmc_boot(void)
(uchar *)CONFIG_SYS_MMC_U_BOOT_DST);
if (err != blk_cnt) {
puts("spl: mmc read failed!!\n");
+#ifndef CONFIG_FSL_CORENET
free(tmp_buf);
+#endif
hang();
}
diff --git a/drivers/mtd/nand/diskonchip.c b/drivers/mtd/nand/diskonchip.c
deleted file mode 100644
index 4cd741e..0000000
--- a/drivers/mtd/nand/diskonchip.c
+++ /dev/null
@@ -1,1780 +0,0 @@
-/*
- * drivers/mtd/nand/diskonchip.c
- *
- * (C) 2003 Red Hat, Inc.
- * (C) 2004 Dan Brown <dan_brown@ieee.org>
- * (C) 2004 Kalev Lember <kalev@smartlink.ee>
- *
- * Author: David Woodhouse <dwmw2@infradead.org>
- * Additional Diskonchip 2000 and Millennium support by Dan Brown <dan_brown@ieee.org>
- * Diskonchip Millennium Plus support by Kalev Lember <kalev@smartlink.ee>
- *
- * Error correction code lifted from the old docecc code
- * Author: Fabrice Bellard (fabrice.bellard@netgem.com)
- * Copyright (C) 2000 Netgem S.A.
- * converted to the generic Reed-Solomon library by Thomas Gleixner <tglx@linutronix.de>
- *
- * Interface to generic NAND code for M-Systems DiskOnChip devices
- */
-
-#include <common.h>
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/delay.h>
-#include <linux/rslib.h>
-#include <linux/moduleparam.h>
-#include <asm/io.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/doc2000.h>
-#include <linux/mtd/compatmac.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/inftl.h>
-
-/* Where to look for the devices? */
-#ifndef CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS
-#define CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS 0
-#endif
-
-static unsigned long __initdata doc_locations[] = {
-#if defined (__alpha__) || defined(__i386__) || defined(__x86_64__)
-#ifdef CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH
- 0xfffc8000, 0xfffca000, 0xfffcc000, 0xfffce000,
- 0xfffd0000, 0xfffd2000, 0xfffd4000, 0xfffd6000,
- 0xfffd8000, 0xfffda000, 0xfffdc000, 0xfffde000,
- 0xfffe0000, 0xfffe2000, 0xfffe4000, 0xfffe6000,
- 0xfffe8000, 0xfffea000, 0xfffec000, 0xfffee000,
-#else /* CONFIG_MTD_DOCPROBE_HIGH */
- 0xc8000, 0xca000, 0xcc000, 0xce000,
- 0xd0000, 0xd2000, 0xd4000, 0xd6000,
- 0xd8000, 0xda000, 0xdc000, 0xde000,
- 0xe0000, 0xe2000, 0xe4000, 0xe6000,
- 0xe8000, 0xea000, 0xec000, 0xee000,
-#endif /* CONFIG_MTD_DOCPROBE_HIGH */
-#else
-#warning Unknown architecture for DiskOnChip. No default probe locations defined
-#endif
- 0xffffffff };
-
-static struct mtd_info *doclist = NULL;
-
-struct doc_priv {
- void __iomem *virtadr;
- unsigned long physadr;
- u_char ChipID;
- u_char CDSNControl;
- int chips_per_floor; /* The number of chips detected on each floor */
- int curfloor;
- int curchip;
- int mh0_page;
- int mh1_page;
- struct mtd_info *nextdoc;
-};
-
-/* This is the syndrome computed by the HW ecc generator upon reading an empty
- page, one with all 0xff for data and stored ecc code. */
-static u_char empty_read_syndrome[6] = { 0x26, 0xff, 0x6d, 0x47, 0x73, 0x7a };
-
-/* This is the ecc value computed by the HW ecc generator upon writing an empty
- page, one with all 0xff for data. */
-static u_char empty_write_ecc[6] = { 0x4b, 0x00, 0xe2, 0x0e, 0x93, 0xf7 };
-
-#define INFTL_BBT_RESERVED_BLOCKS 4
-
-#define DoC_is_MillenniumPlus(doc) ((doc)->ChipID == DOC_ChipID_DocMilPlus16 || (doc)->ChipID == DOC_ChipID_DocMilPlus32)
-#define DoC_is_Millennium(doc) ((doc)->ChipID == DOC_ChipID_DocMil)
-#define DoC_is_2000(doc) ((doc)->ChipID == DOC_ChipID_Doc2k)
-
-static void doc200x_hwcontrol(struct mtd_info *mtd, int cmd,
- unsigned int bitmask);
-static void doc200x_select_chip(struct mtd_info *mtd, int chip);
-
-static int debug = 0;
-module_param(debug, int, 0);
-
-static int try_dword = 1;
-module_param(try_dword, int, 0);
-
-static int no_ecc_failures = 0;
-module_param(no_ecc_failures, int, 0);
-
-static int no_autopart = 0;
-module_param(no_autopart, int, 0);
-
-static int show_firmware_partition = 0;
-module_param(show_firmware_partition, int, 0);
-
-#ifdef CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE
-static int inftl_bbt_write = 1;
-#else
-static int inftl_bbt_write = 0;
-#endif
-module_param(inftl_bbt_write, int, 0);
-
-static unsigned long doc_config_location = CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS;
-module_param(doc_config_location, ulong, 0);
-MODULE_PARM_DESC(doc_config_location, "Physical memory address at which to probe for DiskOnChip");
-
-/* Sector size for HW ECC */
-#define SECTOR_SIZE 512
-/* The sector bytes are packed into NB_DATA 10 bit words */
-#define NB_DATA (((SECTOR_SIZE + 1) * 8 + 6) / 10)
-/* Number of roots */
-#define NROOTS 4
-/* First consective root */
-#define FCR 510
-/* Number of symbols */
-#define NN 1023
-
-/* the Reed Solomon control structure */
-static struct rs_control *rs_decoder;
-
-/*
- * The HW decoder in the DoC ASIC's provides us a error syndrome,
- * which we must convert to a standard syndrome usable by the generic
- * Reed-Solomon library code.
- *
- * Fabrice Bellard figured this out in the old docecc code. I added
- * some comments, improved a minor bit and converted it to make use
- * of the generic Reed-Solomon libary. tglx
- */
-static int doc_ecc_decode(struct rs_control *rs, uint8_t *data, uint8_t *ecc)
-{
- int i, j, nerr, errpos[8];
- uint8_t parity;
- uint16_t ds[4], s[5], tmp, errval[8], syn[4];
-
- /* Convert the ecc bytes into words */
- ds[0] = ((ecc[4] & 0xff) >> 0) | ((ecc[5] & 0x03) << 8);
- ds[1] = ((ecc[5] & 0xfc) >> 2) | ((ecc[2] & 0x0f) << 6);
- ds[2] = ((ecc[2] & 0xf0) >> 4) | ((ecc[3] & 0x3f) << 4);
- ds[3] = ((ecc[3] & 0xc0) >> 6) | ((ecc[0] & 0xff) << 2);
- parity = ecc[1];
-
- /* Initialize the syndrome buffer */
- for (i = 0; i < NROOTS; i++)
- s[i] = ds[0];
- /*
- * Evaluate
- * s[i] = ds[3]x^3 + ds[2]x^2 + ds[1]x^1 + ds[0]
- * where x = alpha^(FCR + i)
- */
- for (j = 1; j < NROOTS; j++) {
- if (ds[j] == 0)
- continue;
- tmp = rs->index_of[ds[j]];
- for (i = 0; i < NROOTS; i++)
- s[i] ^= rs->alpha_to[rs_modnn(rs, tmp + (FCR + i) * j)];
- }
-
- /* Calc s[i] = s[i] / alpha^(v + i) */
- for (i = 0; i < NROOTS; i++) {
- if (syn[i])
- syn[i] = rs_modnn(rs, rs->index_of[s[i]] + (NN - FCR - i));
- }
- /* Call the decoder library */
- nerr = decode_rs16(rs, NULL, NULL, 1019, syn, 0, errpos, 0, errval);
-
- /* Incorrectable errors ? */
- if (nerr < 0)
- return nerr;
-
- /*
- * Correct the errors. The bitpositions are a bit of magic,
- * but they are given by the design of the de/encoder circuit
- * in the DoC ASIC's.
- */
- for (i = 0; i < nerr; i++) {
- int index, bitpos, pos = 1015 - errpos[i];
- uint8_t val;
- if (pos >= NB_DATA && pos < 1019)
- continue;
- if (pos < NB_DATA) {
- /* extract bit position (MSB first) */
- pos = 10 * (NB_DATA - 1 - pos) - 6;
- /* now correct the following 10 bits. At most two bytes
- can be modified since pos is even */
- index = (pos >> 3) ^ 1;
- bitpos = pos & 7;
- if ((index >= 0 && index < SECTOR_SIZE) || index == (SECTOR_SIZE + 1)) {
- val = (uint8_t) (errval[i] >> (2 + bitpos));
- parity ^= val;
- if (index < SECTOR_SIZE)
- data[index] ^= val;
- }
- index = ((pos >> 3) + 1) ^ 1;
- bitpos = (bitpos + 10) & 7;
- if (bitpos == 0)
- bitpos = 8;
- if ((index >= 0 && index < SECTOR_SIZE) || index == (SECTOR_SIZE + 1)) {
- val = (uint8_t) (errval[i] << (8 - bitpos));
- parity ^= val;
- if (index < SECTOR_SIZE)
- data[index] ^= val;
- }
- }
- }
- /* If the parity is wrong, no rescue possible */
- return parity ? -EBADMSG : nerr;
-}
-
-static void DoC_Delay(struct doc_priv *doc, unsigned short cycles)
-{
- volatile char dummy;
- int i;
-
- for (i = 0; i < cycles; i++) {
- if (DoC_is_Millennium(doc))
- dummy = ReadDOC(doc->virtadr, NOP);
- else if (DoC_is_MillenniumPlus(doc))
- dummy = ReadDOC(doc->virtadr, Mplus_NOP);
- else
- dummy = ReadDOC(doc->virtadr, DOCStatus);
- }
-
-}
-
-#define CDSN_CTRL_FR_B_MASK (CDSN_CTRL_FR_B0 | CDSN_CTRL_FR_B1)
-
-/* DOC_WaitReady: Wait for RDY line to be asserted by the flash chip */
-static int _DoC_WaitReady(struct doc_priv *doc)
-{
- void __iomem *docptr = doc->virtadr;
- unsigned long timeo = jiffies + (HZ * 10);
-
- if (debug)
- printk("_DoC_WaitReady...\n");
- /* Out-of-line routine to wait for chip response */
- if (DoC_is_MillenniumPlus(doc)) {
- while ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) {
- if (time_after(jiffies, timeo)) {
- printk("_DoC_WaitReady timed out.\n");
- return -EIO;
- }
- udelay(1);
- cond_resched();
- }
- } else {
- while (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) {
- if (time_after(jiffies, timeo)) {
- printk("_DoC_WaitReady timed out.\n");
- return -EIO;
- }
- udelay(1);
- cond_resched();
- }
- }
-
- return 0;
-}
-
-static inline int DoC_WaitReady(struct doc_priv *doc)
-{
- void __iomem *docptr = doc->virtadr;
- int ret = 0;
-
- if (DoC_is_MillenniumPlus(doc)) {
- DoC_Delay(doc, 4);
-
- if ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK)
- /* Call the out-of-line routine to wait */
- ret = _DoC_WaitReady(doc);
- } else {
- DoC_Delay(doc, 4);
-
- if (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B))
- /* Call the out-of-line routine to wait */
- ret = _DoC_WaitReady(doc);
- DoC_Delay(doc, 2);
- }
-
- if (debug)
- printk("DoC_WaitReady OK\n");
- return ret;
-}
-
-static void doc2000_write_byte(struct mtd_info *mtd, u_char datum)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
-
- if (debug)
- printk("write_byte %02x\n", datum);
- WriteDOC(datum, docptr, CDSNSlowIO);
- WriteDOC(datum, docptr, 2k_CDSN_IO);
-}
-
-static u_char doc2000_read_byte(struct mtd_info *mtd)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
- u_char ret;
-
- ReadDOC(docptr, CDSNSlowIO);
- DoC_Delay(doc, 2);
- ret = ReadDOC(docptr, 2k_CDSN_IO);
- if (debug)
- printk("read_byte returns %02x\n", ret);
- return ret;
-}
-
-static void doc2000_writebuf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
- int i;
- if (debug)
- printk("writebuf of %d bytes: ", len);
- for (i = 0; i < len; i++) {
- WriteDOC_(buf[i], docptr, DoC_2k_CDSN_IO + i);
- if (debug && i < 16)
- printk("%02x ", buf[i]);
- }
- if (debug)
- printk("\n");
-}
-
-static void doc2000_readbuf(struct mtd_info *mtd, u_char *buf, int len)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
- int i;
-
- if (debug)
- printk("readbuf of %d bytes: ", len);
-
- for (i = 0; i < len; i++) {
- buf[i] = ReadDOC(docptr, 2k_CDSN_IO + i);
- }
-}
-
-static void doc2000_readbuf_dword(struct mtd_info *mtd,
- u_char *buf, int len)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
- int i;
-
- if (debug)
- printk("readbuf_dword of %d bytes: ", len);
-
- if (unlikely((((unsigned long)buf) | len) & 3)) {
- for (i = 0; i < len; i++) {
- *(uint8_t *) (&buf[i]) = ReadDOC(docptr, 2k_CDSN_IO + i);
- }
- } else {
- for (i = 0; i < len; i += 4) {
- *(uint32_t*) (&buf[i]) = readl(docptr + DoC_2k_CDSN_IO + i);
- }
- }
-}
-
-static int doc2000_verifybuf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
- int i;
-
- for (i = 0; i < len; i++)
- if (buf[i] != ReadDOC(docptr, 2k_CDSN_IO))
- return -EFAULT;
- return 0;
-}
-
-static uint16_t __init doc200x_ident_chip(struct mtd_info *mtd, int nr)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- uint16_t ret;
-
- doc200x_select_chip(mtd, nr);
- doc200x_hwcontrol(mtd, NAND_CMD_READID,
- NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- doc200x_hwcontrol(mtd, 0, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
- doc200x_hwcontrol(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
-
- /* We cant' use dev_ready here, but at least we wait for the
- * command to complete
- */
- udelay(50);
-
- ret = this->read_byte(mtd) << 8;
- ret |= this->read_byte(mtd);
-
- if (doc->ChipID == DOC_ChipID_Doc2k && try_dword && !nr) {
- /* First chip probe. See if we get same results by 32-bit access */
- union {
- uint32_t dword;
- uint8_t byte[4];
- } ident;
- void __iomem *docptr = doc->virtadr;
-
- doc200x_hwcontrol(mtd, NAND_CMD_READID,
- NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- doc200x_hwcontrol(mtd, 0, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
- doc200x_hwcontrol(mtd, NAND_CMD_NONE,
- NAND_NCE | NAND_CTRL_CHANGE);
-
- udelay(50);
-
- ident.dword = readl(docptr + DoC_2k_CDSN_IO);
- if (((ident.byte[0] << 8) | ident.byte[1]) == ret) {
- printk(KERN_INFO "DiskOnChip 2000 responds to DWORD access\n");
- this->read_buf = &doc2000_readbuf_dword;
- }
- }
-
- return ret;
-}
-
-static void __init doc2000_count_chips(struct mtd_info *mtd)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- uint16_t mfrid;
- int i;
-
- /* Max 4 chips per floor on DiskOnChip 2000 */
- doc->chips_per_floor = 4;
-
- /* Find out what the first chip is */
- mfrid = doc200x_ident_chip(mtd, 0);
-
- /* Find how many chips in each floor. */
- for (i = 1; i < 4; i++) {
- if (doc200x_ident_chip(mtd, i) != mfrid)
- break;
- }
- doc->chips_per_floor = i;
- printk(KERN_DEBUG "Detected %d chips per floor.\n", i);
-}
-
-static int doc200x_wait(struct mtd_info *mtd, struct nand_chip *this)
-{
- struct doc_priv *doc = this->priv;
-
- int status;
-
- DoC_WaitReady(doc);
- this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
- DoC_WaitReady(doc);
- status = (int)this->read_byte(mtd);
-
- return status;
-}
-
-static void doc2001_write_byte(struct mtd_info *mtd, u_char datum)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
-
- WriteDOC(datum, docptr, CDSNSlowIO);
- WriteDOC(datum, docptr, Mil_CDSN_IO);
- WriteDOC(datum, docptr, WritePipeTerm);
-}
-
-static u_char doc2001_read_byte(struct mtd_info *mtd)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
-
- /*ReadDOC(docptr, CDSNSlowIO); */
- /* 11.4.5 -- delay twice to allow extended length cycle */
- DoC_Delay(doc, 2);
- ReadDOC(docptr, ReadPipeInit);
- /*return ReadDOC(docptr, Mil_CDSN_IO); */
- return ReadDOC(docptr, LastDataRead);
-}
-
-static void doc2001_writebuf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
- int i;
-
- for (i = 0; i < len; i++)
- WriteDOC_(buf[i], docptr, DoC_Mil_CDSN_IO + i);
- /* Terminate write pipeline */
- WriteDOC(0x00, docptr, WritePipeTerm);
-}
-
-static void doc2001_readbuf(struct mtd_info *mtd, u_char *buf, int len)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
- int i;
-
- /* Start read pipeline */
- ReadDOC(docptr, ReadPipeInit);
-
- for (i = 0; i < len - 1; i++)
- buf[i] = ReadDOC(docptr, Mil_CDSN_IO + (i & 0xff));
-
- /* Terminate read pipeline */
- buf[i] = ReadDOC(docptr, LastDataRead);
-}
-
-static int doc2001_verifybuf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
- int i;
-
- /* Start read pipeline */
- ReadDOC(docptr, ReadPipeInit);
-
- for (i = 0; i < len - 1; i++)
- if (buf[i] != ReadDOC(docptr, Mil_CDSN_IO)) {
- ReadDOC(docptr, LastDataRead);
- return i;
- }
- if (buf[i] != ReadDOC(docptr, LastDataRead))
- return i;
- return 0;
-}
-
-static u_char doc2001plus_read_byte(struct mtd_info *mtd)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
- u_char ret;
-
- ReadDOC(docptr, Mplus_ReadPipeInit);
- ReadDOC(docptr, Mplus_ReadPipeInit);
- ret = ReadDOC(docptr, Mplus_LastDataRead);
- if (debug)
- printk("read_byte returns %02x\n", ret);
- return ret;
-}
-
-static void doc2001plus_writebuf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
- int i;
-
- if (debug)
- printk("writebuf of %d bytes: ", len);
- for (i = 0; i < len; i++) {
- WriteDOC_(buf[i], docptr, DoC_Mil_CDSN_IO + i);
- if (debug && i < 16)
- printk("%02x ", buf[i]);
- }
- if (debug)
- printk("\n");
-}
-
-static void doc2001plus_readbuf(struct mtd_info *mtd, u_char *buf, int len)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
- int i;
-
- if (debug)
- printk("readbuf of %d bytes: ", len);
-
- /* Start read pipeline */
- ReadDOC(docptr, Mplus_ReadPipeInit);
- ReadDOC(docptr, Mplus_ReadPipeInit);
-
- for (i = 0; i < len - 2; i++) {
- buf[i] = ReadDOC(docptr, Mil_CDSN_IO);
- if (debug && i < 16)
- printk("%02x ", buf[i]);
- }
-
- /* Terminate read pipeline */
- buf[len - 2] = ReadDOC(docptr, Mplus_LastDataRead);
- if (debug && i < 16)
- printk("%02x ", buf[len - 2]);
- buf[len - 1] = ReadDOC(docptr, Mplus_LastDataRead);
- if (debug && i < 16)
- printk("%02x ", buf[len - 1]);
- if (debug)
- printk("\n");
-}
-
-static int doc2001plus_verifybuf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
- int i;
-
- if (debug)
- printk("verifybuf of %d bytes: ", len);
-
- /* Start read pipeline */
- ReadDOC(docptr, Mplus_ReadPipeInit);
- ReadDOC(docptr, Mplus_ReadPipeInit);
-
- for (i = 0; i < len - 2; i++)
- if (buf[i] != ReadDOC(docptr, Mil_CDSN_IO)) {
- ReadDOC(docptr, Mplus_LastDataRead);
- ReadDOC(docptr, Mplus_LastDataRead);
- return i;
- }
- if (buf[len - 2] != ReadDOC(docptr, Mplus_LastDataRead))
- return len - 2;
- if (buf[len - 1] != ReadDOC(docptr, Mplus_LastDataRead))
- return len - 1;
- return 0;
-}
-
-static void doc2001plus_select_chip(struct mtd_info *mtd, int chip)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
- int floor = 0;
-
- if (debug)
- printk("select chip (%d)\n", chip);
-
- if (chip == -1) {
- /* Disable flash internally */
- WriteDOC(0, docptr, Mplus_FlashSelect);
- return;
- }
-
- floor = chip / doc->chips_per_floor;
- chip -= (floor * doc->chips_per_floor);
-
- /* Assert ChipEnable and deassert WriteProtect */
- WriteDOC((DOC_FLASH_CE), docptr, Mplus_FlashSelect);
- this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
-
- doc->curchip = chip;
- doc->curfloor = floor;
-}
-
-static void doc200x_select_chip(struct mtd_info *mtd, int chip)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
- int floor = 0;
-
- if (debug)
- printk("select chip (%d)\n", chip);
-
- if (chip == -1)
- return;
-
- floor = chip / doc->chips_per_floor;
- chip -= (floor * doc->chips_per_floor);
-
- /* 11.4.4 -- deassert CE before changing chip */
- doc200x_hwcontrol(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
-
- WriteDOC(floor, docptr, FloorSelect);
- WriteDOC(chip, docptr, CDSNDeviceSelect);
-
- doc200x_hwcontrol(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
-
- doc->curchip = chip;
- doc->curfloor = floor;
-}
-
-#define CDSN_CTRL_MSK (CDSN_CTRL_CE | CDSN_CTRL_CLE | CDSN_CTRL_ALE)
-
-static void doc200x_hwcontrol(struct mtd_info *mtd, int cmd,
- unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- doc->CDSNControl &= ~CDSN_CTRL_MSK;
- doc->CDSNControl |= ctrl & CDSN_CTRL_MSK;
- if (debug)
- printk("hwcontrol(%d): %02x\n", cmd, doc->CDSNControl);
- WriteDOC(doc->CDSNControl, docptr, CDSNControl);
- /* 11.4.3 -- 4 NOPs after CSDNControl write */
- DoC_Delay(doc, 4);
- }
- if (cmd != NAND_CMD_NONE) {
- if (DoC_is_2000(doc))
- doc2000_write_byte(mtd, cmd);
- else
- doc2001_write_byte(mtd, cmd);
- }
-}
-
-static void doc2001plus_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
-
- /*
- * Must terminate write pipeline before sending any commands
- * to the device.
- */
- if (command == NAND_CMD_PAGEPROG) {
- WriteDOC(0x00, docptr, Mplus_WritePipeTerm);
- WriteDOC(0x00, docptr, Mplus_WritePipeTerm);
- }
-
- /*
- * Write out the command to the device.
- */
- if (command == NAND_CMD_SEQIN) {
- int readcmd;
-
- if (column >= mtd->writesize) {
- /* OOB area */
- column -= mtd->writesize;
- readcmd = NAND_CMD_READOOB;
- } else if (column < 256) {
- /* First 256 bytes --> READ0 */
- readcmd = NAND_CMD_READ0;
- } else {
- column -= 256;
- readcmd = NAND_CMD_READ1;
- }
- WriteDOC(readcmd, docptr, Mplus_FlashCmd);
- }
- WriteDOC(command, docptr, Mplus_FlashCmd);
- WriteDOC(0, docptr, Mplus_WritePipeTerm);
- WriteDOC(0, docptr, Mplus_WritePipeTerm);
-
- if (column != -1 || page_addr != -1) {
- /* Serially input address */
- if (column != -1) {
- /* Adjust columns for 16 bit buswidth */
- if (this->options & NAND_BUSWIDTH_16)
- column >>= 1;
- WriteDOC(column, docptr, Mplus_FlashAddress);
- }
- if (page_addr != -1) {
- WriteDOC((unsigned char)(page_addr & 0xff), docptr, Mplus_FlashAddress);
- WriteDOC((unsigned char)((page_addr >> 8) & 0xff), docptr, Mplus_FlashAddress);
- /* One more address cycle for higher density devices */
- if (this->chipsize & 0x0c000000) {
- WriteDOC((unsigned char)((page_addr >> 16) & 0x0f), docptr, Mplus_FlashAddress);
- printk("high density\n");
- }
- }
- WriteDOC(0, docptr, Mplus_WritePipeTerm);
- WriteDOC(0, docptr, Mplus_WritePipeTerm);
- /* deassert ALE */
- if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
- command == NAND_CMD_READOOB || command == NAND_CMD_READID)
- WriteDOC(0, docptr, Mplus_FlashControl);
- }
-
- /*
- * program and erase have their own busy handlers
- * status and sequential in needs no delay
- */
- switch (command) {
-
- case NAND_CMD_PAGEPROG:
- case NAND_CMD_ERASE1:
- case NAND_CMD_ERASE2:
- case NAND_CMD_SEQIN:
- case NAND_CMD_STATUS:
- return;
-
- case NAND_CMD_RESET:
- if (this->dev_ready)
- break;
- udelay(this->chip_delay);
- WriteDOC(NAND_CMD_STATUS, docptr, Mplus_FlashCmd);
- WriteDOC(0, docptr, Mplus_WritePipeTerm);
- WriteDOC(0, docptr, Mplus_WritePipeTerm);
- while (!(this->read_byte(mtd) & 0x40)) ;
- return;
-
- /* This applies to read commands */
- default:
- /*
- * If we don't have access to the busy pin, we apply the given
- * command delay
- */
- if (!this->dev_ready) {
- udelay(this->chip_delay);
- return;
- }
- }
-
- /* Apply this short delay always to ensure that we do wait tWB in
- * any case on any machine. */
- ndelay(100);
- /* wait until command is processed */
- while (!this->dev_ready(mtd)) ;
-}
-
-static int doc200x_dev_ready(struct mtd_info *mtd)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
-
- if (DoC_is_MillenniumPlus(doc)) {
- /* 11.4.2 -- must NOP four times before checking FR/B# */
- DoC_Delay(doc, 4);
- if ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) {
- if (debug)
- printk("not ready\n");
- return 0;
- }
- if (debug)
- printk("was ready\n");
- return 1;
- } else {
- /* 11.4.2 -- must NOP four times before checking FR/B# */
- DoC_Delay(doc, 4);
- if (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) {
- if (debug)
- printk("not ready\n");
- return 0;
- }
- /* 11.4.2 -- Must NOP twice if it's ready */
- DoC_Delay(doc, 2);
- if (debug)
- printk("was ready\n");
- return 1;
- }
-}
-
-static int doc200x_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
-{
- /* This is our last resort if we couldn't find or create a BBT. Just
- pretend all blocks are good. */
- return 0;
-}
-
-static void doc200x_enable_hwecc(struct mtd_info *mtd, int mode)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
-
- /* Prime the ECC engine */
- switch (mode) {
- case NAND_ECC_READ:
- WriteDOC(DOC_ECC_RESET, docptr, ECCConf);
- WriteDOC(DOC_ECC_EN, docptr, ECCConf);
- break;
- case NAND_ECC_WRITE:
- WriteDOC(DOC_ECC_RESET, docptr, ECCConf);
- WriteDOC(DOC_ECC_EN | DOC_ECC_RW, docptr, ECCConf);
- break;
- }
-}
-
-static void doc2001plus_enable_hwecc(struct mtd_info *mtd, int mode)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
-
- /* Prime the ECC engine */
- switch (mode) {
- case NAND_ECC_READ:
- WriteDOC(DOC_ECC_RESET, docptr, Mplus_ECCConf);
- WriteDOC(DOC_ECC_EN, docptr, Mplus_ECCConf);
- break;
- case NAND_ECC_WRITE:
- WriteDOC(DOC_ECC_RESET, docptr, Mplus_ECCConf);
- WriteDOC(DOC_ECC_EN | DOC_ECC_RW, docptr, Mplus_ECCConf);
- break;
- }
-}
-
-/* This code is only called on write */
-static int doc200x_calculate_ecc(struct mtd_info *mtd, const u_char *dat, unsigned char *ecc_code)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
- int i;
- int emptymatch = 1;
-
- /* flush the pipeline */
- if (DoC_is_2000(doc)) {
- WriteDOC(doc->CDSNControl & ~CDSN_CTRL_FLASH_IO, docptr, CDSNControl);
- WriteDOC(0, docptr, 2k_CDSN_IO);
- WriteDOC(0, docptr, 2k_CDSN_IO);
- WriteDOC(0, docptr, 2k_CDSN_IO);
- WriteDOC(doc->CDSNControl, docptr, CDSNControl);
- } else if (DoC_is_MillenniumPlus(doc)) {
- WriteDOC(0, docptr, Mplus_NOP);
- WriteDOC(0, docptr, Mplus_NOP);
- WriteDOC(0, docptr, Mplus_NOP);
- } else {
- WriteDOC(0, docptr, NOP);
- WriteDOC(0, docptr, NOP);
- WriteDOC(0, docptr, NOP);
- }
-
- for (i = 0; i < 6; i++) {
- if (DoC_is_MillenniumPlus(doc))
- ecc_code[i] = ReadDOC_(docptr, DoC_Mplus_ECCSyndrome0 + i);
- else
- ecc_code[i] = ReadDOC_(docptr, DoC_ECCSyndrome0 + i);
- if (ecc_code[i] != empty_write_ecc[i])
- emptymatch = 0;
- }
- if (DoC_is_MillenniumPlus(doc))
- WriteDOC(DOC_ECC_DIS, docptr, Mplus_ECCConf);
- else
- WriteDOC(DOC_ECC_DIS, docptr, ECCConf);
-#if 0
- /* If emptymatch=1, we might have an all-0xff data buffer. Check. */
- if (emptymatch) {
- /* Note: this somewhat expensive test should not be triggered
- often. It could be optimized away by examining the data in
- the writebuf routine, and remembering the result. */
- for (i = 0; i < 512; i++) {
- if (dat[i] == 0xff)
- continue;
- emptymatch = 0;
- break;
- }
- }
- /* If emptymatch still =1, we do have an all-0xff data buffer.
- Return all-0xff ecc value instead of the computed one, so
- it'll look just like a freshly-erased page. */
- if (emptymatch)
- memset(ecc_code, 0xff, 6);
-#endif
- return 0;
-}
-
-static int doc200x_correct_data(struct mtd_info *mtd, u_char *dat,
- u_char *read_ecc, u_char *isnull)
-{
- int i, ret = 0;
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- void __iomem *docptr = doc->virtadr;
- uint8_t calc_ecc[6];
- volatile u_char dummy;
- int emptymatch = 1;
-
- /* flush the pipeline */
- if (DoC_is_2000(doc)) {
- dummy = ReadDOC(docptr, 2k_ECCStatus);
- dummy = ReadDOC(docptr, 2k_ECCStatus);
- dummy = ReadDOC(docptr, 2k_ECCStatus);
- } else if (DoC_is_MillenniumPlus(doc)) {
- dummy = ReadDOC(docptr, Mplus_ECCConf);
- dummy = ReadDOC(docptr, Mplus_ECCConf);
- dummy = ReadDOC(docptr, Mplus_ECCConf);
- } else {
- dummy = ReadDOC(docptr, ECCConf);
- dummy = ReadDOC(docptr, ECCConf);
- dummy = ReadDOC(docptr, ECCConf);
- }
-
- /* Error occured ? */
- if (dummy & 0x80) {
- for (i = 0; i < 6; i++) {
- if (DoC_is_MillenniumPlus(doc))
- calc_ecc[i] = ReadDOC_(docptr, DoC_Mplus_ECCSyndrome0 + i);
- else
- calc_ecc[i] = ReadDOC_(docptr, DoC_ECCSyndrome0 + i);
- if (calc_ecc[i] != empty_read_syndrome[i])
- emptymatch = 0;
- }
- /* If emptymatch=1, the read syndrome is consistent with an
- all-0xff data and stored ecc block. Check the stored ecc. */
- if (emptymatch) {
- for (i = 0; i < 6; i++) {
- if (read_ecc[i] == 0xff)
- continue;
- emptymatch = 0;
- break;
- }
- }
- /* If emptymatch still =1, check the data block. */
- if (emptymatch) {
- /* Note: this somewhat expensive test should not be triggered
- often. It could be optimized away by examining the data in
- the readbuf routine, and remembering the result. */
- for (i = 0; i < 512; i++) {
- if (dat[i] == 0xff)
- continue;
- emptymatch = 0;
- break;
- }
- }
- /* If emptymatch still =1, this is almost certainly a freshly-
- erased block, in which case the ECC will not come out right.
- We'll suppress the error and tell the caller everything's
- OK. Because it is. */
- if (!emptymatch)
- ret = doc_ecc_decode(rs_decoder, dat, calc_ecc);
- if (ret > 0)
- printk(KERN_ERR "doc200x_correct_data corrected %d errors\n", ret);
- }
- if (DoC_is_MillenniumPlus(doc))
- WriteDOC(DOC_ECC_DIS, docptr, Mplus_ECCConf);
- else
- WriteDOC(DOC_ECC_DIS, docptr, ECCConf);
- if (no_ecc_failures && mtd_is_eccerr(ret)) {
- printk(KERN_ERR "suppressing ECC failure\n");
- ret = 0;
- }
- return ret;
-}
-
-/*u_char mydatabuf[528]; */
-
-/* The strange out-of-order .oobfree list below is a (possibly unneeded)
- * attempt to retain compatibility. It used to read:
- * .oobfree = { {8, 8} }
- * Since that leaves two bytes unusable, it was changed. But the following
- * scheme might affect existing jffs2 installs by moving the cleanmarker:
- * .oobfree = { {6, 10} }
- * jffs2 seems to handle the above gracefully, but the current scheme seems
- * safer. The only problem with it is that any code that parses oobfree must
- * be able to handle out-of-order segments.
- */
-static struct nand_ecclayout doc200x_oobinfo = {
- .eccbytes = 6,
- .eccpos = {0, 1, 2, 3, 4, 5},
- .oobfree = {{8, 8}, {6, 2}}
-};
-
-/* Find the (I)NFTL Media Header, and optionally also the mirror media header.
- On sucessful return, buf will contain a copy of the media header for
- further processing. id is the string to scan for, and will presumably be
- either "ANAND" or "BNAND". If findmirror=1, also look for the mirror media
- header. The page #s of the found media headers are placed in mh0_page and
- mh1_page in the DOC private structure. */
-static int __init find_media_headers(struct mtd_info *mtd, u_char *buf, const char *id, int findmirror)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- unsigned offs;
- int ret;
- size_t retlen;
-
- for (offs = 0; offs < mtd->size; offs += mtd->erasesize) {
- ret = mtd_read(mtd, offs, mtd->writesize, &retlen, buf);
- if (retlen != mtd->writesize)
- continue;
- if (ret) {
- printk(KERN_WARNING "ECC error scanning DOC at 0x%x\n", offs);
- }
- if (memcmp(buf, id, 6))
- continue;
- printk(KERN_INFO "Found DiskOnChip %s Media Header at 0x%x\n", id, offs);
- if (doc->mh0_page == -1) {
- doc->mh0_page = offs >> this->page_shift;
- if (!findmirror)
- return 1;
- continue;
- }
- doc->mh1_page = offs >> this->page_shift;
- return 2;
- }
- if (doc->mh0_page == -1) {
- printk(KERN_WARNING "DiskOnChip %s Media Header not found.\n", id);
- return 0;
- }
- /* Only one mediaheader was found. We want buf to contain a
- mediaheader on return, so we'll have to re-read the one we found. */
- offs = doc->mh0_page << this->page_shift;
- ret = mtd_read(mtd, offs, mtd->writesize, &retlen, buf);
- if (retlen != mtd->writesize) {
- /* Insanity. Give up. */
- printk(KERN_ERR "Read DiskOnChip Media Header once, but can't reread it???\n");
- return 0;
- }
- return 1;
-}
-
-static inline int __init nftl_partscan(struct mtd_info *mtd, struct mtd_partition *parts)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- int ret = 0;
- u_char *buf;
- struct NFTLMediaHeader *mh;
- const unsigned psize = 1 << this->page_shift;
- int numparts = 0;
- unsigned blocks, maxblocks;
- int offs, numheaders;
-
- buf = kmalloc(mtd->writesize, GFP_KERNEL);
- if (!buf) {
- printk(KERN_ERR "DiskOnChip mediaheader kmalloc failed!\n");
- return 0;
- }
- if (!(numheaders = find_media_headers(mtd, buf, "ANAND", 1)))
- goto out;
- mh = (struct NFTLMediaHeader *)buf;
-
- le16_to_cpus(&mh->NumEraseUnits);
- le16_to_cpus(&mh->FirstPhysicalEUN);
- le32_to_cpus(&mh->FormattedSize);
-
- printk(KERN_INFO " DataOrgID = %s\n"
- " NumEraseUnits = %d\n"
- " FirstPhysicalEUN = %d\n"
- " FormattedSize = %d\n"
- " UnitSizeFactor = %d\n",
- mh->DataOrgID, mh->NumEraseUnits,
- mh->FirstPhysicalEUN, mh->FormattedSize,
- mh->UnitSizeFactor);
-
- blocks = mtd->size >> this->phys_erase_shift;
- maxblocks = min(32768U, mtd->erasesize - psize);
-
- if (mh->UnitSizeFactor == 0x00) {
- /* Auto-determine UnitSizeFactor. The constraints are:
- - There can be at most 32768 virtual blocks.
- - There can be at most (virtual block size - page size)
- virtual blocks (because MediaHeader+BBT must fit in 1).
- */
- mh->UnitSizeFactor = 0xff;
- while (blocks > maxblocks) {
- blocks >>= 1;
- maxblocks = min(32768U, (maxblocks << 1) + psize);
- mh->UnitSizeFactor--;
- }
- printk(KERN_WARNING "UnitSizeFactor=0x00 detected. Correct value is assumed to be 0x%02x.\n", mh->UnitSizeFactor);
- }
-
- /* NOTE: The lines below modify internal variables of the NAND and MTD
- layers; variables with have already been configured by nand_scan.
- Unfortunately, we didn't know before this point what these values
- should be. Thus, this code is somewhat dependant on the exact
- implementation of the NAND layer. */
- if (mh->UnitSizeFactor != 0xff) {
- this->bbt_erase_shift += (0xff - mh->UnitSizeFactor);
- mtd->erasesize <<= (0xff - mh->UnitSizeFactor);
- printk(KERN_INFO "Setting virtual erase size to %d\n", mtd->erasesize);
- blocks = mtd->size >> this->bbt_erase_shift;
- maxblocks = min(32768U, mtd->erasesize - psize);
- }
-
- if (blocks > maxblocks) {
- printk(KERN_ERR "UnitSizeFactor of 0x%02x is inconsistent with device size. Aborting.\n", mh->UnitSizeFactor);
- goto out;
- }
-
- /* Skip past the media headers. */
- offs = max(doc->mh0_page, doc->mh1_page);
- offs <<= this->page_shift;
- offs += mtd->erasesize;
-
- if (show_firmware_partition == 1) {
- parts[0].name = " DiskOnChip Firmware / Media Header partition";
- parts[0].offset = 0;
- parts[0].size = offs;
- numparts = 1;
- }
-
- parts[numparts].name = " DiskOnChip BDTL partition";
- parts[numparts].offset = offs;
- parts[numparts].size = (mh->NumEraseUnits - numheaders) << this->bbt_erase_shift;
-
- offs += parts[numparts].size;
- numparts++;
-
- if (offs < mtd->size) {
- parts[numparts].name = " DiskOnChip Remainder partition";
- parts[numparts].offset = offs;
- parts[numparts].size = mtd->size - offs;
- numparts++;
- }
-
- ret = numparts;
- out:
- kfree(buf);
- return ret;
-}
-
-/* This is a stripped-down copy of the code in inftlmount.c */
-static inline int __init inftl_partscan(struct mtd_info *mtd, struct mtd_partition *parts)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- int ret = 0;
- u_char *buf;
- struct INFTLMediaHeader *mh;
- struct INFTLPartition *ip;
- int numparts = 0;
- int blocks;
- int vshift, lastvunit = 0;
- int i;
- int end = mtd->size;
-
- if (inftl_bbt_write)
- end -= (INFTL_BBT_RESERVED_BLOCKS << this->phys_erase_shift);
-
- buf = kmalloc(mtd->writesize, GFP_KERNEL);
- if (!buf) {
- printk(KERN_ERR "DiskOnChip mediaheader kmalloc failed!\n");
- return 0;
- }
-
- if (!find_media_headers(mtd, buf, "BNAND", 0))
- goto out;
- doc->mh1_page = doc->mh0_page + (4096 >> this->page_shift);
- mh = (struct INFTLMediaHeader *)buf;
-
- le32_to_cpus(&mh->NoOfBootImageBlocks);
- le32_to_cpus(&mh->NoOfBinaryPartitions);
- le32_to_cpus(&mh->NoOfBDTLPartitions);
- le32_to_cpus(&mh->BlockMultiplierBits);
- le32_to_cpus(&mh->FormatFlags);
- le32_to_cpus(&mh->PercentUsed);
-
- printk(KERN_INFO " bootRecordID = %s\n"
- " NoOfBootImageBlocks = %d\n"
- " NoOfBinaryPartitions = %d\n"
- " NoOfBDTLPartitions = %d\n"
- " BlockMultiplerBits = %d\n"
- " FormatFlgs = %d\n"
- " OsakVersion = %d.%d.%d.%d\n"
- " PercentUsed = %d\n",
- mh->bootRecordID, mh->NoOfBootImageBlocks,
- mh->NoOfBinaryPartitions,
- mh->NoOfBDTLPartitions,
- mh->BlockMultiplierBits, mh->FormatFlags,
- ((unsigned char *) &mh->OsakVersion)[0] & 0xf,
- ((unsigned char *) &mh->OsakVersion)[1] & 0xf,
- ((unsigned char *) &mh->OsakVersion)[2] & 0xf,
- ((unsigned char *) &mh->OsakVersion)[3] & 0xf,
- mh->PercentUsed);
-
- vshift = this->phys_erase_shift + mh->BlockMultiplierBits;
-
- blocks = mtd->size >> vshift;
- if (blocks > 32768) {
- printk(KERN_ERR "BlockMultiplierBits=%d is inconsistent with device size. Aborting.\n", mh->BlockMultiplierBits);
- goto out;
- }
-
- blocks = doc->chips_per_floor << (this->chip_shift - this->phys_erase_shift);
- if (inftl_bbt_write && (blocks > mtd->erasesize)) {
- printk(KERN_ERR "Writeable BBTs spanning more than one erase block are not yet supported. FIX ME!\n");
- goto out;
- }
-
- /* Scan the partitions */
- for (i = 0; (i < 4); i++) {
- ip = &(mh->Partitions[i]);
- le32_to_cpus(&ip->virtualUnits);
- le32_to_cpus(&ip->firstUnit);
- le32_to_cpus(&ip->lastUnit);
- le32_to_cpus(&ip->flags);
- le32_to_cpus(&ip->spareUnits);
- le32_to_cpus(&ip->Reserved0);
-
- printk(KERN_INFO " PARTITION[%d] ->\n"
- " virtualUnits = %d\n"
- " firstUnit = %d\n"
- " lastUnit = %d\n"
- " flags = 0x%x\n"
- " spareUnits = %d\n",
- i, ip->virtualUnits, ip->firstUnit,
- ip->lastUnit, ip->flags,
- ip->spareUnits);
-
- if ((show_firmware_partition == 1) &&
- (i == 0) && (ip->firstUnit > 0)) {
- parts[0].name = " DiskOnChip IPL / Media Header partition";
- parts[0].offset = 0;
- parts[0].size = mtd->erasesize * ip->firstUnit;
- numparts = 1;
- }
-
- if (ip->flags & INFTL_BINARY)
- parts[numparts].name = " DiskOnChip BDK partition";
- else
- parts[numparts].name = " DiskOnChip BDTL partition";
- parts[numparts].offset = ip->firstUnit << vshift;
- parts[numparts].size = (1 + ip->lastUnit - ip->firstUnit) << vshift;
- numparts++;
- if (ip->lastUnit > lastvunit)
- lastvunit = ip->lastUnit;
- if (ip->flags & INFTL_LAST)
- break;
- }
- lastvunit++;
- if ((lastvunit << vshift) < end) {
- parts[numparts].name = " DiskOnChip Remainder partition";
- parts[numparts].offset = lastvunit << vshift;
- parts[numparts].size = end - parts[numparts].offset;
- numparts++;
- }
- ret = numparts;
- out:
- kfree(buf);
- return ret;
-}
-
-static int __init nftl_scan_bbt(struct mtd_info *mtd)
-{
- int ret, numparts;
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- struct mtd_partition parts[2];
-
- memset((char *)parts, 0, sizeof(parts));
- /* On NFTL, we have to find the media headers before we can read the
- BBTs, since they're stored in the media header eraseblocks. */
- numparts = nftl_partscan(mtd, parts);
- if (!numparts)
- return -EIO;
- this->bbt_td->options = NAND_BBT_ABSPAGE | NAND_BBT_8BIT |
- NAND_BBT_SAVECONTENT | NAND_BBT_WRITE |
- NAND_BBT_VERSION;
- this->bbt_td->veroffs = 7;
- this->bbt_td->pages[0] = doc->mh0_page + 1;
- if (doc->mh1_page != -1) {
- this->bbt_md->options = NAND_BBT_ABSPAGE | NAND_BBT_8BIT |
- NAND_BBT_SAVECONTENT | NAND_BBT_WRITE |
- NAND_BBT_VERSION;
- this->bbt_md->veroffs = 7;
- this->bbt_md->pages[0] = doc->mh1_page + 1;
- } else {
- this->bbt_md = NULL;
- }
-
- /* It's safe to set bd=NULL below because NAND_BBT_CREATE is not set.
- At least as nand_bbt.c is currently written. */
- if ((ret = nand_scan_bbt(mtd, NULL)))
- return ret;
- add_mtd_device(mtd);
-#ifdef CONFIG_MTD_PARTITIONS
- if (!no_autopart)
- add_mtd_partitions(mtd, parts, numparts);
-#endif
- return 0;
-}
-
-static int __init inftl_scan_bbt(struct mtd_info *mtd)
-{
- int ret, numparts;
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
- struct mtd_partition parts[5];
-
- if (this->numchips > doc->chips_per_floor) {
- printk(KERN_ERR "Multi-floor INFTL devices not yet supported.\n");
- return -EIO;
- }
-
- if (DoC_is_MillenniumPlus(doc)) {
- this->bbt_td->options = NAND_BBT_2BIT | NAND_BBT_ABSPAGE;
- if (inftl_bbt_write)
- this->bbt_td->options |= NAND_BBT_WRITE;
- this->bbt_td->pages[0] = 2;
- this->bbt_md = NULL;
- } else {
- this->bbt_td->options = NAND_BBT_LASTBLOCK | NAND_BBT_8BIT | NAND_BBT_VERSION;
- if (inftl_bbt_write)
- this->bbt_td->options |= NAND_BBT_WRITE;
- this->bbt_td->offs = 8;
- this->bbt_td->len = 8;
- this->bbt_td->veroffs = 7;
- this->bbt_td->maxblocks = INFTL_BBT_RESERVED_BLOCKS;
- this->bbt_td->reserved_block_code = 0x01;
- this->bbt_td->pattern = "MSYS_BBT";
-
- this->bbt_md->options = NAND_BBT_LASTBLOCK | NAND_BBT_8BIT | NAND_BBT_VERSION;
- if (inftl_bbt_write)
- this->bbt_md->options |= NAND_BBT_WRITE;
- this->bbt_md->offs = 8;
- this->bbt_md->len = 8;
- this->bbt_md->veroffs = 7;
- this->bbt_md->maxblocks = INFTL_BBT_RESERVED_BLOCKS;
- this->bbt_md->reserved_block_code = 0x01;
- this->bbt_md->pattern = "TBB_SYSM";
- }
-
- /* It's safe to set bd=NULL below because NAND_BBT_CREATE is not set.
- At least as nand_bbt.c is currently written. */
- if ((ret = nand_scan_bbt(mtd, NULL)))
- return ret;
- memset((char *)parts, 0, sizeof(parts));
- numparts = inftl_partscan(mtd, parts);
- /* At least for now, require the INFTL Media Header. We could probably
- do without it for non-INFTL use, since all it gives us is
- autopartitioning, but I want to give it more thought. */
- if (!numparts)
- return -EIO;
- add_mtd_device(mtd);
-#ifdef CONFIG_MTD_PARTITIONS
- if (!no_autopart)
- add_mtd_partitions(mtd, parts, numparts);
-#endif
- return 0;
-}
-
-static inline int __init doc2000_init(struct mtd_info *mtd)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
-
- this->read_byte = doc2000_read_byte;
- this->write_buf = doc2000_writebuf;
- this->read_buf = doc2000_readbuf;
- this->verify_buf = doc2000_verifybuf;
- this->scan_bbt = nftl_scan_bbt;
-
- doc->CDSNControl = CDSN_CTRL_FLASH_IO | CDSN_CTRL_ECC_IO;
- doc2000_count_chips(mtd);
- mtd->name = "DiskOnChip 2000 (NFTL Model)";
- return (4 * doc->chips_per_floor);
-}
-
-static inline int __init doc2001_init(struct mtd_info *mtd)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
-
- this->read_byte = doc2001_read_byte;
- this->write_buf = doc2001_writebuf;
- this->read_buf = doc2001_readbuf;
- this->verify_buf = doc2001_verifybuf;
-
- ReadDOC(doc->virtadr, ChipID);
- ReadDOC(doc->virtadr, ChipID);
- ReadDOC(doc->virtadr, ChipID);
- if (ReadDOC(doc->virtadr, ChipID) != DOC_ChipID_DocMil) {
- /* It's not a Millennium; it's one of the newer
- DiskOnChip 2000 units with a similar ASIC.
- Treat it like a Millennium, except that it
- can have multiple chips. */
- doc2000_count_chips(mtd);
- mtd->name = "DiskOnChip 2000 (INFTL Model)";
- this->scan_bbt = inftl_scan_bbt;
- return (4 * doc->chips_per_floor);
- } else {
- /* Bog-standard Millennium */
- doc->chips_per_floor = 1;
- mtd->name = "DiskOnChip Millennium";
- this->scan_bbt = nftl_scan_bbt;
- return 1;
- }
-}
-
-static inline int __init doc2001plus_init(struct mtd_info *mtd)
-{
- struct nand_chip *this = mtd->priv;
- struct doc_priv *doc = this->priv;
-
- this->read_byte = doc2001plus_read_byte;
- this->write_buf = doc2001plus_writebuf;
- this->read_buf = doc2001plus_readbuf;
- this->verify_buf = doc2001plus_verifybuf;
- this->scan_bbt = inftl_scan_bbt;
- this->cmd_ctrl = NULL;
- this->select_chip = doc2001plus_select_chip;
- this->cmdfunc = doc2001plus_command;
- this->ecc.hwctl = doc2001plus_enable_hwecc;
-
- doc->chips_per_floor = 1;
- mtd->name = "DiskOnChip Millennium Plus";
-
- return 1;
-}
-
-static int __init doc_probe(unsigned long physadr)
-{
- unsigned char ChipID;
- struct mtd_info *mtd;
- struct nand_chip *nand;
- struct doc_priv *doc;
- void __iomem *virtadr;
- unsigned char save_control;
- unsigned char tmp, tmpb, tmpc;
- int reg, len, numchips;
- int ret = 0;
-
- virtadr = ioremap(physadr, DOC_IOREMAP_LEN);
- if (!virtadr) {
- printk(KERN_ERR "Diskonchip ioremap failed: 0x%x bytes at 0x%lx\n", DOC_IOREMAP_LEN, physadr);
- return -EIO;
- }
-
- /* It's not possible to cleanly detect the DiskOnChip - the
- * bootup procedure will put the device into reset mode, and
- * it's not possible to talk to it without actually writing
- * to the DOCControl register. So we store the current contents
- * of the DOCControl register's location, in case we later decide
- * that it's not a DiskOnChip, and want to put it back how we
- * found it.
- */
- save_control = ReadDOC(virtadr, DOCControl);
-
- /* Reset the DiskOnChip ASIC */
- WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_RESET, virtadr, DOCControl);
- WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_RESET, virtadr, DOCControl);
-
- /* Enable the DiskOnChip ASIC */
- WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_NORMAL, virtadr, DOCControl);
- WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_NORMAL, virtadr, DOCControl);
-
- ChipID = ReadDOC(virtadr, ChipID);
-
- switch (ChipID) {
- case DOC_ChipID_Doc2k:
- reg = DoC_2k_ECCStatus;
- break;
- case DOC_ChipID_DocMil:
- reg = DoC_ECCConf;
- break;
- case DOC_ChipID_DocMilPlus16:
- case DOC_ChipID_DocMilPlus32:
- case 0:
- /* Possible Millennium Plus, need to do more checks */
- /* Possibly release from power down mode */
- for (tmp = 0; (tmp < 4); tmp++)
- ReadDOC(virtadr, Mplus_Power);
-
- /* Reset the Millennium Plus ASIC */
- tmp = DOC_MODE_RESET | DOC_MODE_MDWREN | DOC_MODE_RST_LAT | DOC_MODE_BDECT;
- WriteDOC(tmp, virtadr, Mplus_DOCControl);
- WriteDOC(~tmp, virtadr, Mplus_CtrlConfirm);
-
- mdelay(1);
- /* Enable the Millennium Plus ASIC */
- tmp = DOC_MODE_NORMAL | DOC_MODE_MDWREN | DOC_MODE_RST_LAT | DOC_MODE_BDECT;
- WriteDOC(tmp, virtadr, Mplus_DOCControl);
- WriteDOC(~tmp, virtadr, Mplus_CtrlConfirm);
- mdelay(1);
-
- ChipID = ReadDOC(virtadr, ChipID);
-
- switch (ChipID) {
- case DOC_ChipID_DocMilPlus16:
- reg = DoC_Mplus_Toggle;
- break;
- case DOC_ChipID_DocMilPlus32:
- printk(KERN_ERR "DiskOnChip Millennium Plus 32MB is not supported, ignoring.\n");
- default:
- ret = -ENODEV;
- goto notfound;
- }
- break;
-
- default:
- ret = -ENODEV;
- goto notfound;
- }
- /* Check the TOGGLE bit in the ECC register */
- tmp = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT;
- tmpb = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT;
- tmpc = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT;
- if ((tmp == tmpb) || (tmp != tmpc)) {
- printk(KERN_WARNING "Possible DiskOnChip at 0x%lx failed TOGGLE test, dropping.\n", physadr);
- ret = -ENODEV;
- goto notfound;
- }
-
- for (mtd = doclist; mtd; mtd = doc->nextdoc) {
- unsigned char oldval;
- unsigned char newval;
- nand = mtd->priv;
- doc = nand->priv;
- /* Use the alias resolution register to determine if this is
- in fact the same DOC aliased to a new address. If writes
- to one chip's alias resolution register change the value on
- the other chip, they're the same chip. */
- if (ChipID == DOC_ChipID_DocMilPlus16) {
- oldval = ReadDOC(doc->virtadr, Mplus_AliasResolution);
- newval = ReadDOC(virtadr, Mplus_AliasResolution);
- } else {
- oldval = ReadDOC(doc->virtadr, AliasResolution);
- newval = ReadDOC(virtadr, AliasResolution);
- }
- if (oldval != newval)
- continue;
- if (ChipID == DOC_ChipID_DocMilPlus16) {
- WriteDOC(~newval, virtadr, Mplus_AliasResolution);
- oldval = ReadDOC(doc->virtadr, Mplus_AliasResolution);
- WriteDOC(newval, virtadr, Mplus_AliasResolution); /* restore it */
- } else {
- WriteDOC(~newval, virtadr, AliasResolution);
- oldval = ReadDOC(doc->virtadr, AliasResolution);
- WriteDOC(newval, virtadr, AliasResolution); /* restore it */
- }
- newval = ~newval;
- if (oldval == newval) {
- printk(KERN_DEBUG "Found alias of DOC at 0x%lx to 0x%lx\n", doc->physadr, physadr);
- goto notfound;
- }
- }
-
- printk(KERN_NOTICE "DiskOnChip found at 0x%lx\n", physadr);
-
- len = sizeof(struct mtd_info) +
- sizeof(struct nand_chip) + sizeof(struct doc_priv) + (2 * sizeof(struct nand_bbt_descr));
- mtd = kzalloc(len, GFP_KERNEL);
- if (!mtd) {
- printk(KERN_ERR "DiskOnChip kmalloc (%d bytes) failed!\n", len);
- ret = -ENOMEM;
- goto fail;
- }
-
- nand = (struct nand_chip *) (mtd + 1);
- doc = (struct doc_priv *) (nand + 1);
- nand->bbt_td = (struct nand_bbt_descr *) (doc + 1);
- nand->bbt_md = nand->bbt_td + 1;
-
- mtd->priv = nand;
- mtd->owner = THIS_MODULE;
-
- nand->priv = doc;
- nand->select_chip = doc200x_select_chip;
- nand->cmd_ctrl = doc200x_hwcontrol;
- nand->dev_ready = doc200x_dev_ready;
- nand->waitfunc = doc200x_wait;
- nand->block_bad = doc200x_block_bad;
- nand->ecc.hwctl = doc200x_enable_hwecc;
- nand->ecc.calculate = doc200x_calculate_ecc;
- nand->ecc.correct = doc200x_correct_data;
-
- nand->ecc.layout = &doc200x_oobinfo;
- nand->ecc.mode = NAND_ECC_HW_SYNDROME;
- nand->ecc.size = 512;
- nand->ecc.bytes = 6;
- nand->ecc.strength = 2;
- nand->bbt_options = NAND_BBT_USE_FLASH;
-
- doc->physadr = physadr;
- doc->virtadr = virtadr;
- doc->ChipID = ChipID;
- doc->curfloor = -1;
- doc->curchip = -1;
- doc->mh0_page = -1;
- doc->mh1_page = -1;
- doc->nextdoc = doclist;
-
- if (ChipID == DOC_ChipID_Doc2k)
- numchips = doc2000_init(mtd);
- else if (ChipID == DOC_ChipID_DocMilPlus16)
- numchips = doc2001plus_init(mtd);
- else
- numchips = doc2001_init(mtd);
-
- if ((ret = nand_scan(mtd, numchips))) {
- /* DBB note: i believe nand_release is necessary here, as
- buffers may have been allocated in nand_base. Check with
- Thomas. FIX ME! */
- /* nand_release will call del_mtd_device, but we haven't yet
- added it. This is handled without incident by
- del_mtd_device, as far as I can tell. */
- nand_release(mtd);
- kfree(mtd);
- goto fail;
- }
-
- /* Success! */
- doclist = mtd;
- return 0;
-
- notfound:
- /* Put back the contents of the DOCControl register, in case it's not
- actually a DiskOnChip. */
- WriteDOC(save_control, virtadr, DOCControl);
- fail:
- iounmap(virtadr);
- return ret;
-}
-
-static void release_nanddoc(void)
-{
- struct mtd_info *mtd, *nextmtd;
- struct nand_chip *nand;
- struct doc_priv *doc;
-
- for (mtd = doclist; mtd; mtd = nextmtd) {
- nand = mtd->priv;
- doc = nand->priv;
-
- nextmtd = doc->nextdoc;
- nand_release(mtd);
- iounmap(doc->virtadr);
- kfree(mtd);
- }
-}
-
-static int __init init_nanddoc(void)
-{
- int i, ret = 0;
-
- /* We could create the decoder on demand, if memory is a concern.
- * This way we have it handy, if an error happens
- *
- * Symbolsize is 10 (bits)
- * Primitve polynomial is x^10+x^3+1
- * first consecutive root is 510
- * primitve element to generate roots = 1
- * generator polinomial degree = 4
- */
- rs_decoder = init_rs(10, 0x409, FCR, 1, NROOTS);
- if (!rs_decoder) {
- printk(KERN_ERR "DiskOnChip: Could not create a RS decoder\n");
- return -ENOMEM;
- }
-
- if (doc_config_location) {
- printk(KERN_INFO "Using configured DiskOnChip probe address 0x%lx\n", doc_config_location);
- ret = doc_probe(doc_config_location);
- if (ret < 0)
- goto outerr;
- } else {
- for (i = 0; (doc_locations[i] != 0xffffffff); i++) {
- doc_probe(doc_locations[i]);
- }
- }
- /* No banner message any more. Print a message if no DiskOnChip
- found, so the user knows we at least tried. */
- if (!doclist) {
- printk(KERN_INFO "No valid DiskOnChip devices found\n");
- ret = -ENODEV;
- goto outerr;
- }
- return 0;
- outerr:
- free_rs(rs_decoder);
- return ret;
-}
-
-static void __exit cleanup_nanddoc(void)
-{
- /* Cleanup the nand/DoC resources */
- release_nanddoc();
-
- /* Free the reed solomon resources */
- if (rs_decoder) {
- free_rs(rs_decoder);
- }
-}
-
-module_init(init_nanddoc);
-module_exit(cleanup_nanddoc);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
-MODULE_DESCRIPTION("M-Systems DiskOnChip 2000, Millennium and Millennium Plus device driver\n");
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index 2f82f7c..5100772 100644
--- a/drivers/mtd/nand/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -88,11 +88,7 @@ static inline int bad_block(uchar *marker, int port_size)
return __raw_readw((u16 *)marker) != 0xffff;
}
-#ifdef CONFIG_TPL_BUILD
int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
-#else
-static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst)
-#endif
{
struct fsl_ifc *ifc = IFC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
@@ -218,15 +214,6 @@ static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst)
}
/*
- * Defines a static function nand_load_image() here, because non-static makes
- * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
- */
-#ifndef CONFIG_TPL_BUILD
-#define nand_spl_load_image(offs, uboot_size, vdst) \
- nand_load(offs, uboot_size, vdst)
-#endif
-
-/*
* Main entrypoint for NAND Boot. It's necessary that SDRAM is already
* configured and available since this code loads the main U-boot image
* from NAND into SDRAM and starts from there.
diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c
index e5ac79b..b915469 100644
--- a/drivers/mtd/spi/fsl_espi_spl.c
+++ b/drivers/mtd/spi/fsl_espi_spl.c
@@ -12,6 +12,20 @@
#define ESPI_BOOT_IMAGE_ADDR 0x50
#define CONFIG_CFG_DATA_SECTOR 0
+void spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst)
+{
+ struct spi_flash *flash;
+
+ flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+ CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+ if (flash == NULL) {
+ puts("\nspi_flash_probe failed");
+ hang();
+ }
+
+ spi_flash_read(flash, offs, size, vdst);
+}
+
/*
* The main entry for SPI booting. It's necessary that SDRAM is already
* configured and available since this code loads the main U-Boot image
@@ -20,8 +34,10 @@
void spi_boot(void)
{
void (*uboot)(void) __noreturn;
- u32 offset, code_len;
+ u32 offset, code_len, copy_len = 0;
+#ifndef CONFIG_FSL_CORENET
unsigned char *buf = NULL;
+#endif
struct spi_flash *flash;
flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
@@ -56,8 +72,15 @@ void spi_boot(void)
code_len = code_len - CONFIG_SPL_MAX_SIZE;
#endif
/* copy code to DDR */
- spi_flash_read(flash, offset, code_len,
- (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_DST);
+ printf("Loading second stage boot loader ");
+ while (copy_len <= code_len) {
+ spi_flash_read(flash, offset + copy_len, 0x2000,
+ (void *)(CONFIG_SYS_SPI_FLASH_U_BOOT_DST
+ + copy_len));
+ copy_len = copy_len + 0x2000;
+ putc('.');
+ }
+
/*
* Jump to U-Boot image
*/
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 9a66e68..9d9b259 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -4532,7 +4532,6 @@ static int e1000_set_phy_type (struct e1000_hw *hw)
hw->mac_type == e1000_82547 ||
hw->mac_type == e1000_82547_rev_2) {
hw->phy_type = e1000_phy_igp;
- hw->phy_type = e1000_phy_igp;
break;
}
case IGP03E1000_E_PHY_ID:
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index bca20b3..400e9dd 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -350,16 +350,16 @@ int fm_init_common(int index, struct ccsr_fman *reg)
{
int rc;
#if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
- void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR;
+ void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
- rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_ADDR,
+ rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
&fw_length, (u_char *)addr);
if (rc == -EUCLEAN) {
printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
- CONFIG_SYS_QE_FMAN_FW_ADDR, rc);
+ CONFIG_SYS_FMAN_FW_ADDR, rc);
}
#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
struct spi_flash *ucode_flash;
@@ -371,7 +371,7 @@ int fm_init_common(int index, struct ccsr_fman *reg)
if (!ucode_flash)
printf("SF: probe for ucode failed\n");
else {
- ret = spi_flash_read(ucode_flash, CONFIG_SYS_QE_FMAN_FW_ADDR,
+ ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR,
CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
if (ret)
printf("SF: read for ucode failed\n");
@@ -381,7 +381,7 @@ int fm_init_common(int index, struct ccsr_fman *reg)
int dev = CONFIG_SYS_MMC_ENV_DEV;
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
- u32 blk = CONFIG_SYS_QE_FMAN_FW_ADDR / 512;
+ u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
if (!mmc)
@@ -395,7 +395,7 @@ int fm_init_common(int index, struct ccsr_fman *reg)
flush_cache((ulong)addr, cnt * 512);
}
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
- void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR;
+ void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
#else
void *addr = NULL;
#endif
diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
index 140e59b..2f4bc11 100644
--- a/drivers/net/fm/memac_phy.c
+++ b/drivers/net/fm/memac_phy.c
@@ -133,5 +133,17 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
bus->priv = info->regs;
+ /*
+ * On some platforms like B4860, default value of MDIO_CLK_DIV bits
+ * in mdio_stat(mdio_cfg) register generates MDIO clock too high
+ * (much higher than 2.5MHz), violating the IEEE specs.
+ * On other platforms like T1040, default value of MDIO_CLK_DIV bits
+ * is zero, so MDIO clock is disabled.
+ * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
+ * be properly initialized.
+ */
+ setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat,
+ MDIO_STAT_CLKDIV(258));
+
return mdio_register(bus);
}
diff --git a/drivers/net/inca-ip_sw.c b/drivers/net/inca-ip_sw.c
deleted file mode 100644
index cdfbfa6..0000000
--- a/drivers/net/inca-ip_sw.c
+++ /dev/null
@@ -1,793 +0,0 @@
-/*
- * INCA-IP internal switch ethernet driver.
- *
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <common.h>
-
-#include <malloc.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/inca-ip.h>
-#include <asm/addrspace.h>
-
-
-#define NUM_RX_DESC PKTBUFSRX
-#define NUM_TX_DESC 3
-#define TOUT_LOOP 1000000
-
-
-#define DELAY udelay(10000)
- /* Sometimes the store word instruction hangs while writing to one
- * of the Switch registers. Moving the instruction into a separate
- * function somehow makes the problem go away.
- */
-static void SWORD(volatile u32 * reg, u32 value)
-{
- *reg = value;
-}
-
-#define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value;
-#define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
-#define SW_WRITE_REG(reg, value) \
- SWORD(reg, value);\
- DELAY;\
- SWORD(reg, value);
-
-#define SW_READ_REG(reg, value) \
- value = (u32)*((volatile u32*)reg);\
- DELAY;\
- value = (u32)*((volatile u32*)reg);
-
-#define INCA_DMA_TX_POLLING_TIME 0x07
-#define INCA_DMA_RX_POLLING_TIME 0x07
-
-#define INCA_DMA_TX_HOLD 0x80000000
-#define INCA_DMA_TX_EOP 0x40000000
-#define INCA_DMA_TX_SOP 0x20000000
-#define INCA_DMA_TX_ICPT 0x10000000
-#define INCA_DMA_TX_IEOP 0x08000000
-
-#define INCA_DMA_RX_C 0x80000000
-#define INCA_DMA_RX_SOP 0x40000000
-#define INCA_DMA_RX_EOP 0x20000000
-
-#define INCA_SWITCH_PHY_SPEED_10H 0x1
-#define INCA_SWITCH_PHY_SPEED_10F 0x5
-#define INCA_SWITCH_PHY_SPEED_100H 0x2
-#define INCA_SWITCH_PHY_SPEED_100F 0x6
-
-/************************ Auto MDIX settings ************************/
-#define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR
-#define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL
-#define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT
-#define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16
-
-#define WAIT_SIGNAL_RETRIES 100
-#define WAIT_LINK_RETRIES 100
-#define LINK_RETRY_DELAY 2000 /* ms */
-/********************************************************************/
-
-typedef struct
-{
- union {
- struct {
- volatile u32 HOLD :1;
- volatile u32 ICpt :1;
- volatile u32 IEop :1;
- volatile u32 offset :3;
- volatile u32 reserved0 :4;
- volatile u32 NFB :22;
- }field;
-
- volatile u32 word;
- }params;
-
- volatile u32 nextRxDescPtr;
-
- volatile u32 RxDataPtr;
-
- union {
- struct {
- volatile u32 C :1;
- volatile u32 Sop :1;
- volatile u32 Eop :1;
- volatile u32 reserved3 :12;
- volatile u32 NBT :17;
- }field;
-
- volatile u32 word;
- }status;
-
-} inca_rx_descriptor_t;
-
-
-typedef struct
-{
- union {
- struct {
- volatile u32 HOLD :1;
- volatile u32 Eop :1;
- volatile u32 Sop :1;
- volatile u32 ICpt :1;
- volatile u32 IEop :1;
- volatile u32 reserved0 :5;
- volatile u32 NBA :22;
- }field;
-
- volatile u32 word;
- }params;
-
- volatile u32 nextTxDescPtr;
-
- volatile u32 TxDataPtr;
-
- volatile u32 C :1;
- volatile u32 reserved3 :31;
-
-} inca_tx_descriptor_t;
-
-
-static inca_rx_descriptor_t rx_ring[NUM_RX_DESC] __attribute__ ((aligned(16)));
-static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16)));
-
-static int tx_new, rx_new, tx_hold, rx_hold;
-static int tx_old_hold = -1;
-static int initialized = 0;
-
-
-static int inca_switch_init(struct eth_device *dev, bd_t * bis);
-static int inca_switch_send(struct eth_device *dev, void *packet, int length);
-static int inca_switch_recv(struct eth_device *dev);
-static void inca_switch_halt(struct eth_device *dev);
-static void inca_init_switch_chip(void);
-static void inca_dma_init(void);
-static int inca_amdix(void);
-
-
-int inca_switch_initialize(bd_t * bis)
-{
- struct eth_device *dev;
-
-#if 0
- printf("Entered inca_switch_initialize()\n");
-#endif
-
- if (!(dev = (struct eth_device *) malloc (sizeof *dev))) {
- printf("Failed to allocate memory\n");
- return 0;
- }
- memset(dev, 0, sizeof(*dev));
-
- inca_dma_init();
-
- inca_init_switch_chip();
-
-#if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
- inca_amdix();
-#endif
-
- sprintf(dev->name, "INCA-IP Switch");
- dev->init = inca_switch_init;
- dev->halt = inca_switch_halt;
- dev->send = inca_switch_send;
- dev->recv = inca_switch_recv;
-
- eth_register(dev);
-
-#if 0
- printf("Leaving inca_switch_initialize()\n");
-#endif
-
- return 0;
-}
-
-
-static int inca_switch_init(struct eth_device *dev, bd_t * bis)
-{
- int i;
- u32 v, regValue;
- u16 wTmp;
-
-#if 0
- printf("Entering inca_switch_init()\n");
-#endif
-
- /* Set MAC address.
- */
- wTmp = (u16)dev->enetaddr[0];
- regValue = (wTmp << 8) | dev->enetaddr[1];
-
- SW_WRITE_REG(INCA_IP_Switch_PMAC_SA1, regValue);
-
- wTmp = (u16)dev->enetaddr[2];
- regValue = (wTmp << 8) | dev->enetaddr[3];
- regValue = regValue << 16;
- wTmp = (u16)dev->enetaddr[4];
- regValue |= (wTmp<<8) | dev->enetaddr[5];
-
- SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue);
-
- /* Initialize the descriptor rings.
- */
- for (i = 0; i < NUM_RX_DESC; i++) {
- inca_rx_descriptor_t * rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[i]);
- memset(rx_desc, 0, sizeof(rx_ring[i]));
-
- /* Set maximum size of receive buffer.
- */
- rx_desc->params.field.NFB = PKTSIZE_ALIGN;
-
- /* Set the offset of the receive buffer. Zero means
- * that the offset mechanism is not used.
- */
- rx_desc->params.field.offset = 0;
-
- /* Check if it is the last descriptor.
- */
- if (i == (NUM_RX_DESC - 1)) {
- /* Let the last descriptor point to the first
- * one.
- */
- rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(rx_ring);
- } else {
- /* Set the address of the next descriptor.
- */
- rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(&rx_ring[i+1]);
- }
-
- rx_desc->RxDataPtr = (u32)CKSEG1ADDR(NetRxPackets[i]);
- }
-
-#if 0
- printf("rx_ring = 0x%08X 0x%08X\n", (u32)rx_ring, (u32)&rx_ring[0]);
- printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]);
-#endif
-
- for (i = 0; i < NUM_TX_DESC; i++) {
- inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[i]);
-
- memset(tx_desc, 0, sizeof(tx_ring[i]));
-
- tx_desc->params.word = 0;
- tx_desc->params.field.HOLD = 1;
- tx_desc->C = 1;
-
- /* Check if it is the last descriptor.
- */
- if (i == (NUM_TX_DESC - 1)) {
- /* Let the last descriptor point to the
- * first one.
- */
- tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(tx_ring);
- } else {
- /* Set the address of the next descriptor.
- */
- tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(&tx_ring[i+1]);
- }
- }
-
- /* Initialize RxDMA.
- */
- DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v);
- debug("RX status = 0x%08X\n", v);
-
- /* Writing to the FRDA of CHANNEL.
- */
- DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring);
-
- /* Writing to the COMMAND REG.
- */
- DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_INIT);
-
- /* Initialize TxDMA.
- */
- DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v);
- debug("TX status = 0x%08X\n", v);
-
- /* Writing to the FRDA of CHANNEL.
- */
- DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring);
-
- tx_new = rx_new = 0;
-
- tx_hold = NUM_TX_DESC - 1;
- rx_hold = NUM_RX_DESC - 1;
-
-#if 0
- rx_ring[rx_hold].params.field.HOLD = 1;
-#endif
- /* enable spanning tree forwarding, enable the CPU port */
- /* ST_PT:
- * CPS (CPU port status) 0x3 (forwarding)
- * LPS (LAN port status) 0x3 (forwarding)
- * PPS (PC port status) 0x3 (forwarding)
- */
- SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f);
-
-#if 0
- printf("Leaving inca_switch_init()\n");
-#endif
-
- return 0;
-}
-
-
-static int inca_switch_send(struct eth_device *dev, void *packet, int length)
-{
- int i;
- int res = -1;
- u32 command;
- u32 regValue;
- inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_new]);
-
-#if 0
- printf("Entered inca_switch_send()\n");
-#endif
-
- if (length <= 0) {
- printf ("%s: bad packet size: %d\n", dev->name, length);
- goto Done;
- }
-
- for(i = 0; tx_desc->C == 0; i++) {
- if (i >= TOUT_LOOP) {
- printf("%s: tx error buffer not ready\n", dev->name);
- goto Done;
- }
- }
-
- if (tx_old_hold >= 0) {
- ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_old_hold]))->params.field.HOLD = 1;
- }
- tx_old_hold = tx_hold;
-
- tx_desc->params.word =
- (INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD);
-
- tx_desc->C = 0;
- tx_desc->TxDataPtr = (u32)packet;
- tx_desc->params.field.NBA = length;
-
- ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->params.field.HOLD = 0;
-
- tx_hold = tx_new;
- tx_new = (tx_new + 1) % NUM_TX_DESC;
-
-
- if (! initialized) {
- command = INCA_IP_DMA_DMA_TXCCR0_INIT;
- initialized = 1;
- } else {
- command = INCA_IP_DMA_DMA_TXCCR0_HR;
- }
-
- DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
- regValue |= command;
-#if 0
- printf("regValue = 0x%x\n", regValue);
-#endif
- DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
-
-#if 1
- for(i = 0; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->C == 0; i++) {
- if (i >= TOUT_LOOP) {
- printf("%s: tx buffer not ready\n", dev->name);
- goto Done;
- }
- }
-#endif
- res = length;
-Done:
-#if 0
- printf("Leaving inca_switch_send()\n");
-#endif
- return res;
-}
-
-
-static int inca_switch_recv(struct eth_device *dev)
-{
- int length = 0;
- inca_rx_descriptor_t * rx_desc;
-
-#if 0
- printf("Entered inca_switch_recv()\n");
-#endif
-
- for (;;) {
- rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_new]);
-
- if (rx_desc->status.field.C == 0) {
- break;
- }
-
-#if 0
- rx_ring[rx_new].params.field.HOLD = 1;
-#endif
-
- if (! rx_desc->status.field.Eop) {
- printf("Partly received packet!!!\n");
- break;
- }
-
- length = rx_desc->status.field.NBT;
- rx_desc->status.word &=
- ~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C);
-#if 0
-{
- int i;
- for (i=0;i<length - 4;i++) {
- if (i % 16 == 0) printf("\n%04x: ", i);
- printf("%02X ", NetRxPackets[rx_new][i]);
- }
- printf("\n");
-}
-#endif
-
- if (length) {
-#if 0
- printf("Received %d bytes\n", length);
-#endif
- NetReceive((void*)CKSEG1ADDR(NetRxPackets[rx_new]), length - 4);
- } else {
-#if 1
- printf("Zero length!!!\n");
-#endif
- }
-
-
- ((inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_hold]))->params.field.HOLD = 0;
-
- rx_hold = rx_new;
-
- rx_new = (rx_new + 1) % NUM_RX_DESC;
- }
-
-#if 0
- printf("Leaving inca_switch_recv()\n");
-#endif
-
- return length;
-}
-
-
-static void inca_switch_halt(struct eth_device *dev)
-{
-#if 0
- printf("Entered inca_switch_halt()\n");
-#endif
-
-#if 1
- initialized = 0;
-#endif
-#if 1
- /* Disable forwarding to the CPU port.
- */
- SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
-
- /* Close RxDMA channel.
- */
- DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
-
- /* Close TxDMA channel.
- */
- DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF);
-
-
-#endif
-#if 0
- printf("Leaving inca_switch_halt()\n");
-#endif
-}
-
-
-static void inca_init_switch_chip(void)
-{
- u32 regValue;
-
- /* To workaround a problem with collision counter
- * (see Errata sheet).
- */
- SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001);
- SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001);
-
-#if 1
- /* init MDIO configuration:
- * MDS (Poll speed): 0x01 (4ms)
- * PHY_LAN_ADDR: 0x06
- * PHY_PC_ADDR: 0x05
- * UEP (Use External PHY): 0x00 (Internal PHY is used)
- * PS (Port Select): 0x00 (PT/UMM for LAN)
- * PT (PHY Test): 0x00 (no test mode)
- * UMM (Use MDIO Mode): 0x00 (state machine is disabled)
- */
- SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50);
-
- /* init PHY:
- * SL (Auto Neg. Speed for LAN)
- * SP (Auto Neg. Speed for PC)
- * LL (Link Status for LAN)
- * LP (Link Status for PC)
- * DL (Duplex Status for LAN)
- * DP (Duplex Status for PC)
- * PL (Auto Neg. Pause Status for LAN)
- * PP (Auto Neg. Pause Status for PC)
- */
- SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff);
-
- /* MDIO_ACC:
- * RA (Request/Ack) 0x01 (Request)
- * RW (Read/Write) 0x01 (Write)
- * PHY_ADDR 0x05 (PC)
- * REG_ADDR 0x00 (PHY_BCR: basic control register)
- * PHY_DATA 0x8000
- * Reset - software reset
- * LB (loop back) - normal
- * SS (speed select) - 10 Mbit/s
- * ANE (auto neg. enable) - enable
- * PD (power down) - normal
- * ISO (isolate) - normal
- * RAN (restart auto neg.) - normal
- * DM (duplex mode) - half duplex
- * CT (collision test) - enable
- */
- SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000);
-
- /* MDIO_ACC:
- * RA (Request/Ack) 0x01 (Request)
- * RW (Read/Write) 0x01 (Write)
- * PHY_ADDR 0x06 (LAN)
- * REG_ADDR 0x00 (PHY_BCR: basic control register)
- * PHY_DATA 0x8000
- * Reset - software reset
- * LB (loop back) - normal
- * SS (speed select) - 10 Mbit/s
- * ANE (auto neg. enable) - enable
- * PD (power down) - normal
- * ISO (isolate) - normal
- * RAN (restart auto neg.) - normal
- * DM (duplex mode) - half duplex
- * CT (collision test) - enable
- */
- SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000);
-
-#endif
-
- /* Make sure the CPU port is disabled for now. We
- * don't want packets to get stacked for us until
- * we enable DMA and are prepared to receive them.
- */
- SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
-
- SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue);
-
- /* CRC GEN is enabled.
- */
- regValue |= 0x00000200;
- SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue);
-
- /* ADD TAG is disabled.
- */
- SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
- regValue &= ~0x00000002;
- SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
-}
-
-
-static void inca_dma_init(void)
-{
- /* Switch off all DMA channels.
- */
- DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
- DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF);
-
- DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
- DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF);
- DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF);
-
- /* Setup TX channel polling time.
- */
- DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME);
-
- /* Setup RX channel polling time.
- */
- DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME);
-
- /* ERRATA: write reset value into the DMA RX IMR register.
- */
- DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF);
-
- /* Just in case: disable all transmit interrupts also.
- */
- DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF);
-
- DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF);
- DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF);
-}
-
-#if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
-static int inca_amdix(void)
-{
- u32 phyReg1 = 0;
- u32 phyReg4 = 0;
- u32 phyReg5 = 0;
- u32 phyReg6 = 0;
- u32 phyReg31 = 0;
- u32 regEphy = 0;
- int mdi_flag;
- int retries;
-
- /* Setup GPIO pins.
- */
- *INCA_IP_AUTO_MDIX_LAN_PORTS_DIR |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
- *INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
-
-#if 0
- /* Wait for signal.
- */
- retries = WAIT_SIGNAL_RETRIES;
- while (--retries) {
- SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
- (0x1 << 31) | /* RA */
- (0x0 << 30) | /* Read */
- (0x6 << 21) | /* LAN */
- (17 << 16)); /* PHY_MCSR */
- do {
- SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
- } while (phyReg1 & (1 << 31));
-
- if (phyReg1 & (1 << 1)) {
- /* Signal detected */
- break;
- }
- }
-
- if (!retries)
- goto Fail;
-#endif
-
- /* Set MDI mode.
- */
- *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
- mdi_flag = 1;
-
- /* Wait for link.
- */
- retries = WAIT_LINK_RETRIES;
- while (--retries) {
- udelay(LINK_RETRY_DELAY * 1000);
- SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
- (0x1 << 31) | /* RA */
- (0x0 << 30) | /* Read */
- (0x6 << 21) | /* LAN */
- (1 << 16)); /* PHY_BSR */
- do {
- SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
- } while (phyReg1 & (1 << 31));
-
- if (phyReg1 & (1 << 2)) {
- /* Link is up */
- break;
- } else if (mdi_flag) {
- /* Set MDIX mode */
- *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
- mdi_flag = 0;
- } else {
- /* Set MDI mode */
- *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
- mdi_flag = 1;
- }
- }
-
- if (!retries) {
- goto Fail;
- } else {
- SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
- (0x1 << 31) | /* RA */
- (0x0 << 30) | /* Read */
- (0x6 << 21) | /* LAN */
- (1 << 16)); /* PHY_BSR */
- do {
- SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
- } while (phyReg1 & (1 << 31));
-
- /* Auto-negotiation / Parallel detection complete
- */
- if (phyReg1 & (1 << 5)) {
- SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
- (0x1 << 31) | /* RA */
- (0x0 << 30) | /* Read */
- (0x6 << 21) | /* LAN */
- (31 << 16)); /* PHY_SCSR */
- do {
- SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31);
- } while (phyReg31 & (1 << 31));
-
- switch ((phyReg31 >> 2) & 0x7) {
- case INCA_SWITCH_PHY_SPEED_10H:
- /* 10Base-T Half-duplex */
- regEphy = 0;
- break;
- case INCA_SWITCH_PHY_SPEED_10F:
- /* 10Base-T Full-duplex */
- regEphy = INCA_IP_Switch_EPHY_DL;
- break;
- case INCA_SWITCH_PHY_SPEED_100H:
- /* 100Base-TX Half-duplex */
- regEphy = INCA_IP_Switch_EPHY_SL;
- break;
- case INCA_SWITCH_PHY_SPEED_100F:
- /* 100Base-TX Full-duplex */
- regEphy = INCA_IP_Switch_EPHY_SL | INCA_IP_Switch_EPHY_DL;
- break;
- }
-
- /* In case of Auto-negotiation,
- * update the negotiated PAUSE support status
- */
- if (phyReg1 & (1 << 3)) {
- SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
- (0x1 << 31) | /* RA */
- (0x0 << 30) | /* Read */
- (0x6 << 21) | /* LAN */
- (6 << 16)); /* MII_EXPANSION */
- do {
- SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6);
- } while (phyReg6 & (1 << 31));
-
- /* We are Autoneg-able.
- * Is Link partner also able to autoneg?
- */
- if (phyReg6 & (1 << 0)) {
- SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
- (0x1 << 31) | /* RA */
- (0x0 << 30) | /* Read */
- (0x6 << 21) | /* LAN */
- (4 << 16)); /* MII_ADVERTISE */
- do {
- SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4);
- } while (phyReg4 & (1 << 31));
-
- /* We advertise PAUSE capab.
- * Does link partner also advertise it?
- */
- if (phyReg4 & (1 << 10)) {
- SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
- (0x1 << 31) | /* RA */
- (0x0 << 30) | /* Read */
- (0x6 << 21) | /* LAN */
- (5 << 16)); /* MII_LPA */
- do {
- SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5);
- } while (phyReg5 & (1 << 31));
-
- /* Link partner is PAUSE capab.
- */
- if (phyReg5 & (1 << 10)) {
- regEphy |= INCA_IP_Switch_EPHY_PL;
- }
- }
- }
-
- }
-
- /* Link is up */
- regEphy |= INCA_IP_Switch_EPHY_LL;
-
- SW_WRITE_REG(INCA_IP_Switch_EPHY, regEphy);
- }
- }
-
- return 0;
-
-Fail:
- printf("No Link on LAN port\n");
- return -1;
-}
-#endif /* CONFIG_INCA_IP_SWITCH_AMDIX */
diff --git a/drivers/net/lan91c96.h b/drivers/net/lan91c96.h
index 2f0d640..3e914ce 100644
--- a/drivers/net/lan91c96.h
+++ b/drivers/net/lan91c96.h
@@ -58,13 +58,7 @@ typedef unsigned long int dword;
#ifdef CONFIG_CPU_PXA25X
-#ifdef CONFIG_LUBBOCK
-#define SMC_IO_SHIFT 2
-#undef USE_32_BIT
-
-#else
#define SMC_IO_SHIFT 0
-#endif
#define SMCREG(edev, r) ((edev)->iobase+((r)<<SMC_IO_SHIFT))
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index 71a3110..237fbba 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -71,12 +71,16 @@ struct pcnet_init_block {
u32 reserved2;
};
-typedef struct pcnet_priv {
+struct pcnet_uncached_priv {
struct pcnet_rx_head rx_ring[RX_RING_SIZE];
struct pcnet_tx_head tx_ring[TX_RING_SIZE];
struct pcnet_init_block init_block;
+};
+
+typedef struct pcnet_priv {
+ struct pcnet_uncached_priv *uc;
/* Receive Buffer space */
- unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
+ unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4];
int cur_rx;
int cur_tx;
} pcnet_priv_t;
@@ -283,6 +287,7 @@ static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
static int pcnet_init(struct eth_device *dev, bd_t *bis)
{
+ struct pcnet_uncached_priv *uc;
int i, val;
u32 addr;
@@ -325,24 +330,35 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10);
addr = (addr + 0xf) & ~0xf;
lp = (pcnet_priv_t *)addr;
+
+ addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->uc));
+ flush_dcache_range(addr, addr + sizeof(*lp->uc));
+ addr = UNCACHED_SDRAM(addr);
+ lp->uc = (struct pcnet_uncached_priv *)addr;
+
+ addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->rx_buf));
+ flush_dcache_range(addr, addr + sizeof(*lp->rx_buf));
+ lp->rx_buf = (void *)addr;
}
- lp->init_block.mode = cpu_to_le16(0x0000);
- lp->init_block.filter[0] = 0x00000000;
- lp->init_block.filter[1] = 0x00000000;
+ uc = lp->uc;
+
+ uc->init_block.mode = cpu_to_le16(0x0000);
+ uc->init_block.filter[0] = 0x00000000;
+ uc->init_block.filter[1] = 0x00000000;
/*
* Initialize the Rx ring.
*/
lp->cur_rx = 0;
for (i = 0; i < RX_RING_SIZE; i++) {
- lp->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]);
- lp->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
- lp->rx_ring[i].status = cpu_to_le16(0x8000);
+ uc->rx_ring[i].base = PCI_TO_MEM_LE(dev, (*lp->rx_buf)[i]);
+ uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
+ uc->rx_ring[i].status = cpu_to_le16(0x8000);
PCNET_DEBUG1
("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
- lp->rx_ring[i].base, lp->rx_ring[i].buf_length,
- lp->rx_ring[i].status);
+ uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
+ uc->rx_ring[i].status);
}
/*
@@ -351,34 +367,34 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
*/
lp->cur_tx = 0;
for (i = 0; i < TX_RING_SIZE; i++) {
- lp->tx_ring[i].base = 0;
- lp->tx_ring[i].status = 0;
+ uc->tx_ring[i].base = 0;
+ uc->tx_ring[i].status = 0;
}
/*
* Setup Init Block.
*/
- PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->init_block);
+ PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
for (i = 0; i < 6; i++) {
- lp->init_block.phys_addr[i] = dev->enetaddr[i];
- PCNET_DEBUG1(" %02x", lp->init_block.phys_addr[i]);
+ lp->uc->init_block.phys_addr[i] = dev->enetaddr[i];
+ PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
}
- lp->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
+ uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
RX_RING_LEN_BITS);
- lp->init_block.rx_ring = PCI_TO_MEM_LE(dev, lp->rx_ring);
- lp->init_block.tx_ring = PCI_TO_MEM_LE(dev, lp->tx_ring);
- flush_dcache_range((unsigned long)lp, (unsigned long)&lp->rx_buf);
+ uc->init_block.rx_ring = PCI_TO_MEM_LE(dev, uc->rx_ring);
+ uc->init_block.tx_ring = PCI_TO_MEM_LE(dev, uc->tx_ring);
PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
- lp->init_block.tlen_rlen,
- lp->init_block.rx_ring, lp->init_block.tx_ring);
+ uc->init_block.tlen_rlen,
+ uc->init_block.rx_ring, uc->init_block.tx_ring);
/*
* Tell the controller where the Init Block is located.
*/
- addr = PCI_TO_MEM(dev, &lp->init_block);
+ barrier();
+ addr = PCI_TO_MEM(dev, &lp->uc->init_block);
pcnet_write_csr(dev, 1, addr & 0xffff);
pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
@@ -408,7 +424,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
{
int i, status;
- struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx];
+ struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
packet);
@@ -418,9 +434,7 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
/* Wait for completion by testing the OWN bit */
for (i = 1000; i > 0; i--) {
- invalidate_dcache_range((unsigned long)entry,
- (unsigned long)entry + sizeof(*entry));
- status = le16_to_cpu(entry->status);
+ status = readw(&entry->status);
if ((status & 0x8000) == 0)
break;
udelay(100);
@@ -437,13 +451,10 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
* Setup Tx ring. Caution: the write order is important here,
* set the status with the "ownership" bits last.
*/
- status = 0x8300;
- entry->length = cpu_to_le16(-pkt_len);
- entry->misc = 0x00000000;
- entry->base = PCI_TO_MEM_LE(dev, packet);
- entry->status = cpu_to_le16(status);
- flush_dcache_range((unsigned long)entry,
- (unsigned long)entry + sizeof(*entry));
+ writew(-pkt_len, &entry->length);
+ writel(0, &entry->misc);
+ writel(PCI_TO_MEM(dev, packet), &entry->base);
+ writew(0x8300, &entry->status);
/* Trigger an immediate send poll. */
pcnet_write_csr(dev, 0, 0x0008);
@@ -459,54 +470,51 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
static int pcnet_recv (struct eth_device *dev)
{
struct pcnet_rx_head *entry;
+ unsigned char *buf;
int pkt_len = 0;
- u16 status;
+ u16 status, err_status;
while (1) {
- entry = &lp->rx_ring[lp->cur_rx];
- invalidate_dcache_range((unsigned long)entry,
- (unsigned long)entry + sizeof(*entry));
+ entry = &lp->uc->rx_ring[lp->cur_rx];
/*
* If we own the next entry, it's a new packet. Send it up.
*/
- status = le16_to_cpu(entry->status);
+ status = readw(&entry->status);
if ((status & 0x8000) != 0)
break;
- status >>= 8;
+ err_status = status >> 8;
- if (status != 0x03) { /* There was an error. */
+ if (err_status != 0x03) { /* There was an error. */
printf("%s: Rx%d", dev->name, lp->cur_rx);
- PCNET_DEBUG1(" (status=0x%x)", status);
- if (status & 0x20)
+ PCNET_DEBUG1(" (status=0x%x)", err_status);
+ if (err_status & 0x20)
printf(" Frame");
- if (status & 0x10)
+ if (err_status & 0x10)
printf(" Overflow");
- if (status & 0x08)
+ if (err_status & 0x08)
printf(" CRC");
- if (status & 0x04)
+ if (err_status & 0x04)
printf(" Fifo");
printf(" Error\n");
- entry->status &= le16_to_cpu(0x03ff);
+ status &= 0x03ff;
} else {
- pkt_len = (le32_to_cpu(entry->msg_length) & 0xfff) - 4;
+ pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
if (pkt_len < 60) {
printf("%s: Rx%d: invalid packet length %d\n",
dev->name, lp->cur_rx, pkt_len);
} else {
- invalidate_dcache_range(
- (unsigned long)lp->rx_buf[lp->cur_rx],
- (unsigned long)lp->rx_buf[lp->cur_rx] +
- pkt_len);
- NetReceive(lp->rx_buf[lp->cur_rx], pkt_len);
+ buf = (*lp->rx_buf)[lp->cur_rx];
+ invalidate_dcache_range((unsigned long)buf,
+ (unsigned long)buf + pkt_len);
+ NetReceive(buf, pkt_len);
PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
- lp->cur_rx, pkt_len,
- lp->rx_buf[lp->cur_rx]);
+ lp->cur_rx, pkt_len, buf);
}
}
- entry->status |= cpu_to_le16(0x8000);
- flush_dcache_range((unsigned long)entry,
- (unsigned long)entry + sizeof(*entry));
+
+ status |= 0x8000;
+ writew(status, &entry->status);
if (++lp->cur_rx >= RX_RING_SIZE)
lp->cur_rx = 0;
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index b80980d..abd4e5b 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -53,7 +53,7 @@ static struct phy_driver AR8031_driver = {
.uid = 0x4dd074,
.mask = 0xffffffef,
.features = PHY_GBIT_FEATURES,
- .config = genphy_config,
+ .config = ar8021_config,
.startup = genphy_startup,
.shutdown = genphy_shutdown,
};
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index c555979..3a55d27 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -296,7 +296,7 @@ static struct phy_driver VSC8574_driver = {
static struct phy_driver VSC8514_driver = {
.name = "Vitesse VSC8514",
- .uid = 0x70570,
+ .uid = 0x70670,
.mask = 0xffff0,
.features = PHY_GBIT_FEATURES,
.config = &vsc8514_config,
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 101489c..3cadd23 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -11,6 +11,7 @@
#include <common.h>
#include <net.h>
+#include <netdev.h>
#include <config.h>
#include <fdtdec.h>
#include <libfdt.h>
@@ -338,7 +339,8 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
phy_detection(dev);
/* interface - look at tsec */
- phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
+ phydev = phy_connect(priv->bus, priv->phyaddr, dev,
+ PHY_INTERFACE_MODE_MII);
phydev->supported = supported | ADVERTISED_Pause |
ADVERTISED_Asym_Pause;
diff --git a/drivers/pcmcia/mpc8xx_pcmcia.c b/drivers/pcmcia/mpc8xx_pcmcia.c
index 3732583..6638277 100644
--- a/drivers/pcmcia/mpc8xx_pcmcia.c
+++ b/drivers/pcmcia/mpc8xx_pcmcia.c
@@ -211,7 +211,7 @@ static u_int m8xx_get_graycode(u_int size)
#if 0
-#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
+#if defined(CONFIG_RPXLITE)
/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
* SYPCR is write once only, therefore must the slowest memory be faster
diff --git a/drivers/pcmcia/rpx_pcmcia.c b/drivers/pcmcia/rpx_pcmcia.c
index c7c425b..5b24f0b 100644
--- a/drivers/pcmcia/rpx_pcmcia.c
+++ b/drivers/pcmcia/rpx_pcmcia.c
@@ -18,7 +18,7 @@
#endif
#if defined(CONFIG_PCMCIA) \
- && (defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE))
+ && defined(CONFIG_RPXLITE)
#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
@@ -70,4 +70,4 @@ static int pcmcia_hardware_disable(int slot)
#endif
-#endif /* CONFIG_PCMCIA && (CONFIG_RPXCLASSIC || CONFIG_RPXLITE) */
+#endif /* CONFIG_PCMCIA && CONFIG_RPXLITE */
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index b5ddc4b..b1da75e 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -165,7 +165,7 @@ void qe_init(uint qe_base)
/*
* Upload microcode to IRAM for those SOCs which do not have ROM in QE.
*/
- qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR);
+ qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
/* enable the microcode in IRAM */
out_be32(&qe_immr->iram.iready,QE_IRAM_READY);
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index c82ac7b..ebb7c5f 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -282,5 +282,7 @@ int qe_set_mii_clk_src(int ucc_num);
int qe_upload_firmware(const struct qe_firmware *firmware);
struct qe_firmware_info *qe_get_firmware_info(void);
void ft_qe_setup(void *blob);
+void qe_init(uint qe_base);
+void qe_reset(void);
#endif /* __QE_H__ */
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index df05bde..c4fb59c 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -117,7 +117,7 @@ serial_initfunc(ns16550_serial_initialize);
serial_initfunc(pxa_serial_initialize);
serial_initfunc(s3c24xx_serial_initialize);
serial_initfunc(s5p_serial_initialize);
-serial_initfunc(zynq_serial_initalize);
+serial_initfunc(zynq_serial_initialize);
serial_initfunc(bfin_serial_initialize);
serial_initfunc(bfin_jtag_initialize);
serial_initfunc(mpc512x_serial_initialize);
@@ -214,7 +214,7 @@ void serial_initialize(void)
bfin_serial_initialize();
bfin_jtag_initialize();
uartlite_serial_initialize();
- zynq_serial_initalize();
+ zynq_serial_initialize();
au1x00_serial_initialize();
asc_serial_initialize();
jz_serial_initialize();
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index 53a8af0..1ff27d5 100644
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -153,17 +153,17 @@ static int uart_zynq_serial_getc(const int port)
/* Multi serial device functions */
#define DECLARE_PSSERIAL_FUNCTIONS(port) \
- int uart_zynq##port##_init(void) \
+ static int uart_zynq##port##_init(void) \
{ return uart_zynq_serial_init(port); } \
- void uart_zynq##port##_setbrg(void) \
+ static void uart_zynq##port##_setbrg(void) \
{ return uart_zynq_serial_setbrg(port); } \
- int uart_zynq##port##_getc(void) \
+ static int uart_zynq##port##_getc(void) \
{ return uart_zynq_serial_getc(port); } \
- int uart_zynq##port##_tstc(void) \
+ static int uart_zynq##port##_tstc(void) \
{ return uart_zynq_serial_tstc(port); } \
- void uart_zynq##port##_putc(const char c) \
+ static void uart_zynq##port##_putc(const char c) \
{ uart_zynq_serial_putc(c, port); } \
- void uart_zynq##port##_puts(const char *s) \
+ static void uart_zynq##port##_puts(const char *s) \
{ uart_zynq_serial_puts(s, port); }
/* Serial device descriptor */
@@ -179,10 +179,10 @@ static int uart_zynq_serial_getc(const int port)
}
DECLARE_PSSERIAL_FUNCTIONS(0);
-struct serial_device uart_zynq_serial0_device =
+static struct serial_device uart_zynq_serial0_device =
INIT_PSSERIAL_STRUCTURE(0, "ttyPS0");
DECLARE_PSSERIAL_FUNCTIONS(1);
-struct serial_device uart_zynq_serial1_device =
+static struct serial_device uart_zynq_serial1_device =
INIT_PSSERIAL_STRUCTURE(1, "ttyPS1");
#ifdef CONFIG_OF_CONTROL
@@ -223,7 +223,7 @@ __weak struct serial_device *default_serial_console(void)
}
#endif
-void zynq_serial_initalize(void)
+void zynq_serial_initialize(void)
{
serial_register(&uart_zynq_serial0_device);
serial_register(&uart_zynq_serial1_device);
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 804a2bd..896c8d4 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -13,6 +13,7 @@ ifdef CONFIG_USB_GADGET
obj-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o
obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o
obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o
+obj-$(CONFIG_CI_UDC) += ci_udc.o
obj-$(CONFIG_THOR_FUNCTION) += f_thor.o
obj-$(CONFIG_USBDOWNLOAD_GADGET) += g_dnl.o
obj-$(CONFIG_DFU_FUNCTION) += f_dfu.o
diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c
index 14b1e9b..02d3fda 100644
--- a/drivers/usb/gadget/ci_udc.c
+++ b/drivers/usb/gadget/ci_udc.c
@@ -321,7 +321,7 @@ static void ci_debounce(struct ci_ep *ep, int in)
if (addr == ba)
return; /* not a bounce */
- memcpy(ep->req.buf, ep->b_buf, ep->req.length);
+ memcpy(ep->req.buf, ep->b_buf, ep->req.actual);
free:
/* Large payloads use allocated buffer, free it. */
if (ep->b_buf != ep->b_fast)
@@ -350,6 +350,9 @@ static int ci_ep_queue(struct usb_ep *ep,
item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE;
item->page0 = (uint32_t)ci_ep->b_buf;
item->page1 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x1000;
+ item->page2 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x2000;
+ item->page3 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x3000;
+ item->page4 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x4000;
ci_flush_qtd(num);
head->next = (unsigned) item;
@@ -385,7 +388,7 @@ static void handle_ep_complete(struct ci_ep *ep)
num, in ? "in" : "out", item->info, item->page0);
len = (item->info >> 16) & 0x7fff;
- ep->req.length -= len;
+ ep->req.actual = ep->req.length - len;
ci_debounce(ep, in);
DBG("ept%d %s complete %x\n",
@@ -413,7 +416,11 @@ static void handle_setup(void)
ci_invalidate_qh(0);
memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest));
+#ifdef CONFIG_CI_UDC_HAS_HOSTPC
+ writel(EPT_RX(0), &udc->epsetupstat);
+#else
writel(EPT_RX(0), &udc->epstat);
+#endif
DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest),
r.bRequestType, r.bRequest, r.wIndex, r.wValue);
@@ -480,6 +487,9 @@ static void stop_activity(void)
struct ept_queue_head *head;
struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
writel(readl(&udc->epcomp), &udc->epcomp);
+#ifdef CONFIG_CI_UDC_HAS_HOSTPC
+ writel(readl(&udc->epsetupstat), &udc->epsetupstat);
+#endif
writel(readl(&udc->epstat), &udc->epstat);
writel(0xffffffff, &udc->epflush);
@@ -521,7 +531,11 @@ void udc_irq(void)
int max = 64;
int speed = USB_SPEED_FULL;
+#ifdef CONFIG_CI_UDC_HAS_HOSTPC
+ bit = (readl(&udc->hostpc1_devlc) >> 25) & 3;
+#else
bit = (readl(&udc->portsc) >> 26) & 3;
+#endif
DBG("-- portchange %x %s\n", bit, (bit == 2) ? "High" : "Full");
if (bit == 2) {
speed = USB_SPEED_HIGH;
@@ -538,7 +552,11 @@ void udc_irq(void)
printf("<UEI %x>\n", readl(&udc->epcomp));
if ((n & STS_UI) || (n & STS_UEI)) {
+#ifdef CONFIG_CI_UDC_HAS_HOSTPC
+ n = readl(&udc->epsetupstat);
+#else
n = readl(&udc->epstat);
+#endif
if (n & EPT_RX(0))
handle_setup();
@@ -699,7 +717,6 @@ static int ci_udc_probe(void)
int usb_gadget_register_driver(struct usb_gadget_driver *driver)
{
- struct ci_udc *udc;
int ret;
if (!driver)
@@ -714,12 +731,18 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
return ret;
ret = ci_udc_probe();
+#if defined(CONFIG_USB_EHCI_MX6) || defined(CONFIG_USB_EHCI_MXS)
+ /*
+ * FIXME: usb_lowlevel_init()->ehci_hcd_init() should be doing all
+ * HW-specific initialization, e.g. ULPI-vs-UTMI PHY selection
+ */
if (!ret) {
- udc = (struct ci_udc *)controller.ctrl->hcor;
+ struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
/* select ULPI phy */
writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc);
}
+#endif
ret = driver->bind(&controller.gadget);
if (ret) {
diff --git a/drivers/usb/gadget/ci_udc.h b/drivers/usb/gadget/ci_udc.h
index 42f6ef4..4425fd9 100644
--- a/drivers/usb/gadget/ci_udc.h
+++ b/drivers/usb/gadget/ci_udc.h
@@ -8,45 +8,74 @@
#define NUM_ENDPOINTS 6
+#ifdef CONFIG_CI_UDC_HAS_HOSTPC
+struct ci_udc {
+ u32 usbcmd; /* 0x130 */
+ u32 usbsts; /* 0x134 */
+ u32 pad1[3];
+ u32 devaddr; /* 0x144 */
+ u32 epinitaddr; /* 0x148 */
+ u32 pad2[10];
+ u32 portsc; /* 0x174 */
+ u32 pad178[(0x1b4 - (0x174 + 4)) / 4];
+ u32 hostpc1_devlc; /* 0x1b4 */
+ u32 pad1b8[(0x1f8 - (0x1b4 + 4)) / 4];
+ u32 usbmode; /* 0x1f8 */
+ u32 pad1fc[(0x208 - (0x1f8 + 4)) / 4];
+ u32 epsetupstat; /* 0x208 */
+ u32 epprime; /* 0x20c */
+ u32 epflush; /* 0x210 */
+ u32 epstat; /* 0x214 */
+ u32 epcomp; /* 0x218 */
+ u32 epctrl[16]; /* 0x21c */
+};
+#else
struct ci_udc {
-#define MICRO_8FRAME 0x8
-#define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16)
-#define USBCMD_FS2 (1 << 15)
-#define USBCMD_RST (1 << 1)
-#define USBCMD_RUN (1)
u32 usbcmd; /* 0x140 */
-#define STS_SLI (1 << 8)
-#define STS_URI (1 << 6)
-#define STS_PCI (1 << 2)
-#define STS_UEI (1 << 1)
-#define STS_UI (1 << 0)
u32 usbsts; /* 0x144 */
u32 pad1[3];
u32 devaddr; /* 0x154 */
u32 epinitaddr; /* 0x158 */
u32 pad2[10];
-#define PTS_ENABLE 2
-#define PTS(x) (((x) & 0x3) << 30)
-#define PFSC (1 << 24)
u32 portsc; /* 0x184 */
u32 pad3[8];
-#define USBMODE_DEVICE 2
u32 usbmode; /* 0x1a8 */
u32 epstat; /* 0x1ac */
-#define EPT_TX(x) (1 << (((x) & 0xffff) + 16))
-#define EPT_RX(x) (1 << ((x) & 0xffff))
u32 epprime; /* 0x1b0 */
u32 epflush; /* 0x1b4 */
u32 pad4;
u32 epcomp; /* 0x1bc */
+ u32 epctrl[16]; /* 0x1c0 */
+};
+
+#define PTS_ENABLE 2
+#define PTS(x) (((x) & 0x3) << 30)
+#define PFSC (1 << 24)
+#endif
+
+#define MICRO_8FRAME 0x8
+#define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16)
+#define USBCMD_FS2 (1 << 15)
+#define USBCMD_RST (1 << 1)
+#define USBCMD_RUN (1)
+
+#define STS_SLI (1 << 8)
+#define STS_URI (1 << 6)
+#define STS_PCI (1 << 2)
+#define STS_UEI (1 << 1)
+#define STS_UI (1 << 0)
+
+#define USBMODE_DEVICE 2
+
+#define EPT_TX(x) (1 << (((x) & 0xffff) + 16))
+#define EPT_RX(x) (1 << ((x) & 0xffff))
+
#define CTRL_TXE (1 << 23)
#define CTRL_TXR (1 << 22)
#define CTRL_RXE (1 << 7)
#define CTRL_RXR (1 << 6)
#define CTRL_TXT_BULK (2 << 18)
#define CTRL_RXT_BULK (2 << 2)
- u32 epctrl[16]; /* 0x1c0 */
-};
struct ci_ep {
struct usb_ep ep;
diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c
index de75ff1..1b1e179 100644
--- a/drivers/usb/gadget/f_dfu.c
+++ b/drivers/usb/gadget/f_dfu.c
@@ -24,6 +24,7 @@
#include <linux/usb/composite.h>
#include <dfu.h>
+#include <g_dnl.h>
#include "f_dfu.h"
struct f_dfu {
@@ -817,3 +818,5 @@ int dfu_add(struct usb_configuration *c)
return dfu_bind_config(c);
}
+
+DECLARE_GADGET_BIND_CALLBACK(usb_dnl_dfu, dfu_add);
diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
index f896169..6374bb9 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -243,7 +243,7 @@
#include <config.h>
#include <malloc.h>
#include <common.h>
-#include <usb.h>
+#include <g_dnl.h>
#include <linux/err.h>
#include <linux/usb/ch9.h>
@@ -255,6 +255,7 @@
#include <linux/usb/gadget.h>
#include <linux/usb/composite.h>
#include <usb/lin_gadget_compat.h>
+#include <g_dnl.h>
/*------------------------------------------------------------------------*/
@@ -680,11 +681,11 @@ static int sleep_thread(struct fsg_common *common)
/* Handle CTRL+C */
if (ctrlc())
return -EPIPE;
-#ifdef CONFIG_USB_CABLE_CHECK
+
/* Check cable connection */
- if (!usb_cable_connected())
+ if (!g_dnl_board_usb_cable_connected())
return -EIO;
-#endif
+
k = 0;
}
@@ -2778,3 +2779,5 @@ int fsg_init(struct ums *ums_dev)
return 0;
}
+
+DECLARE_GADGET_BIND_CALLBACK(usb_dnl_ums, fsg_add);
diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c
index f5c0224..feef9e4 100644
--- a/drivers/usb/gadget/f_thor.c
+++ b/drivers/usb/gadget/f_thor.c
@@ -204,14 +204,14 @@ static long long int download_head(unsigned long long total,
static int download_tail(long long int left, int cnt)
{
+ struct dfu_entity *dfu_entity = dfu_get_entity(alt_setting_num);
void *transfer_buffer = dfu_get_buf();
int ret;
debug("%s: left: %llu cnt: %d\n", __func__, left, cnt);
if (left) {
- ret = dfu_write(dfu_get_entity(alt_setting_num),
- transfer_buffer, left, cnt++);
+ ret = dfu_write(dfu_entity, transfer_buffer, left, cnt++);
if (ret) {
error("DFU write failed [%d]: left: %llu", ret, left);
return ret;
@@ -225,11 +225,16 @@ static int download_tail(long long int left, int cnt)
* This also frees memory malloc'ed by dfu_get_buf(), so no explicit
* need fo call dfu_free_buf() is needed.
*/
- ret = dfu_write(dfu_get_entity(alt_setting_num),
- transfer_buffer, 0, cnt);
+ ret = dfu_write(dfu_entity, transfer_buffer, 0, cnt);
if (ret)
error("DFU write failed [%d] cnt: %d", ret, cnt);
+ ret = dfu_flush(dfu_entity, transfer_buffer, 0, cnt);
+ if (ret) {
+ error("DFU flush failed!");
+ return ret;
+ }
+
return ret;
}
@@ -999,3 +1004,5 @@ int thor_add(struct usb_configuration *c)
debug("%s:\n", __func__);
return thor_func_init(c);
}
+
+DECLARE_GADGET_BIND_CALLBACK(usb_dnl_thor, thor_add);
diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c
index dd95afe..25611ac 100644
--- a/drivers/usb/gadget/g_dnl.c
+++ b/drivers/usb/gadget/g_dnl.c
@@ -41,7 +41,6 @@
#define DRIVER_VERSION "usb_dnl 2.0"
-static const char shortname[] = "usb_dnl_";
static const char product[] = "USB download gadget";
static char g_dnl_serial[MAX_STRING_SERIAL];
static const char manufacturer[] = CONFIG_G_DNL_MANUFACTURER;
@@ -96,29 +95,36 @@ static int g_dnl_unbind(struct usb_composite_dev *cdev)
free(cdev->config);
cdev->config = NULL;
debug("%s: calling usb_gadget_disconnect for "
- "controller '%s'\n", shortname, gadget->name);
+ "controller '%s'\n", __func__, gadget->name);
usb_gadget_disconnect(gadget);
return 0;
}
+static inline struct g_dnl_bind_callback *g_dnl_bind_callback_first(void)
+{
+ return ll_entry_start(struct g_dnl_bind_callback,
+ g_dnl_bind_callbacks);
+}
+
+static inline struct g_dnl_bind_callback *g_dnl_bind_callback_end(void)
+{
+ return ll_entry_end(struct g_dnl_bind_callback,
+ g_dnl_bind_callbacks);
+}
+
static int g_dnl_do_config(struct usb_configuration *c)
{
const char *s = c->cdev->driver->name;
- int ret = -1;
+ struct g_dnl_bind_callback *callback = g_dnl_bind_callback_first();
debug("%s: configuration: 0x%p composite dev: 0x%p\n",
__func__, c, c->cdev);
- printf("GADGET DRIVER: %s\n", s);
- if (!strcmp(s, "usb_dnl_dfu"))
- ret = dfu_add(c);
- else if (!strcmp(s, "usb_dnl_ums"))
- ret = fsg_add(c);
- else if (!strcmp(s, "usb_dnl_thor"))
- ret = thor_add(c);
-
- return ret;
+ for (; callback != g_dnl_bind_callback_end(); callback++)
+ if (!strcmp(s, callback->usb_function_name))
+ return callback->fptr(c);
+ return -ENODEV;
}
static int g_dnl_config_register(struct usb_composite_dev *cdev)
@@ -152,6 +158,11 @@ __weak int g_dnl_get_board_bcd_device_number(int gcnum)
return gcnum;
}
+__weak int g_dnl_board_usb_cable_connected(void)
+{
+ return -EOPNOTSUPP;
+}
+
static int g_dnl_get_bcd_device_number(struct usb_composite_dev *cdev)
{
struct usb_gadget *gadget = cdev->gadget;
@@ -203,12 +214,12 @@ static int g_dnl_bind(struct usb_composite_dev *cdev)
device_desc.bcdDevice = cpu_to_le16(gcnum);
else {
debug("%s: controller '%s' not recognized\n",
- shortname, gadget->name);
+ __func__, gadget->name);
device_desc.bcdDevice = __constant_cpu_to_le16(0x9999);
}
debug("%s: calling usb_gadget_connect for "
- "controller '%s'\n", shortname, gadget->name);
+ "controller '%s'\n", __func__, gadget->name);
usb_gadget_connect(gadget);
return 0;
@@ -227,36 +238,23 @@ static struct usb_composite_driver g_dnl_driver = {
.unbind = g_dnl_unbind,
};
-int g_dnl_register(const char *type)
+/*
+ * NOTICE:
+ * Registering via USB function name won't be necessary after rewriting
+ * g_dnl to support multiple USB functions.
+ */
+int g_dnl_register(const char *name)
{
- /* The largest function name is 4 */
- static char name[sizeof(shortname) + 4];
int ret;
- if (!strcmp(type, "dfu")) {
- strcpy(name, shortname);
- strcat(name, type);
- } else if (!strcmp(type, "ums")) {
- strcpy(name, shortname);
- strcat(name, type);
- } else if (!strcmp(type, "thor")) {
- strcpy(name, shortname);
- strcat(name, type);
- } else {
- printf("%s: unknown command: %s\n", __func__, type);
- return -EINVAL;
- }
-
+ debug("%s: g_dnl_driver.name = %s\n", __func__, name);
g_dnl_driver.name = name;
- debug("%s: g_dnl_driver.name: %s\n", __func__, g_dnl_driver.name);
ret = usb_composite_register(&g_dnl_driver);
-
if (ret) {
printf("%s: failed!, error: %d\n", __func__, ret);
return ret;
}
-
return 0;
}
diff --git a/drivers/usb/gadget/storage_common.c b/drivers/usb/gadget/storage_common.c
index 02803df..7430074 100644
--- a/drivers/usb/gadget/storage_common.c
+++ b/drivers/usb/gadget/storage_common.c
@@ -311,7 +311,11 @@ static struct fsg_lun *fsg_lun_from_dev(struct device *dev)
#define DELAYED_STATUS (EP0_BUFSIZE + 999) /* An impossibly large value */
/* Number of buffers we will use. 2 is enough for double-buffering */
+#ifndef CONFIG_CI_UDC
#define FSG_NUM_BUFFERS 2
+#else
+#define FSG_NUM_BUFFERS 1 /* ci_udc only allows 1 req per ep at present */
+#endif
/* Default size of buffer length. */
#define FSG_BUFLEN ((u32)16384)
diff --git a/drivers/usb/gadget/usbstring.c b/drivers/usb/gadget/usbstring.c
index de5fa3f..8c3ff64 100644
--- a/drivers/usb/gadget/usbstring.c
+++ b/drivers/usb/gadget/usbstring.c
@@ -108,6 +108,9 @@ usb_gadget_get_string(struct usb_gadget_strings *table, int id, u8 *buf)
struct usb_string *s;
int len;
+ if (!table)
+ return -EINVAL;
+
/* descriptor 0 has the language id */
if (id == 0) {
buf[0] = 4;
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 578b097..b301e28 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
+obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
# xhci
obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index 9356878..edd91a8 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -197,7 +197,8 @@ int ehci_hcd_init(int index, enum usb_init_type init,
#ifdef CONFIG_OF_CONTROL
/* setup the Vbus gpio here */
- if (!fdtdec_setup_gpio(&ctx->vbus_gpio))
+ if (fdt_gpio_isvalid(&ctx->vbus_gpio) &&
+ !fdtdec_setup_gpio(&ctx->vbus_gpio))
gpio_direction_output(ctx->vbus_gpio.gpio, 1);
#endif
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 1ca7cf5..6cb4d98 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -14,9 +14,12 @@
#include <asm/io.h>
#include <usb/ehci-fsl.h>
#include <hwconfig.h>
+#include <asm/fsl_errata.h>
#include "ehci.h"
+static void set_txfifothresh(struct usb_ehci *, u32);
+
/* Check USB PHY clock valid */
static int usb_phy_clk_valid(struct usb_ehci *ehci)
{
@@ -41,11 +44,23 @@ int ehci_hcd_init(int index, enum usb_init_type init,
struct usb_ehci *ehci = NULL;
const char *phy_type = NULL;
size_t len;
+ char current_usb_controller[5];
#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
char usb_phy[5];
usb_phy[0] = '\0';
#endif
+ if (has_erratum_a007075()) {
+ /*
+ * A 5ms delay is needed after applying soft-reset to the
+ * controller to let external ULPI phy come out of reset.
+ * This delay needs to be added before re-initializing
+ * the controller after soft-resetting completes
+ */
+ mdelay(5);
+ }
+ memset(current_usb_controller, '\0', 5);
+ snprintf(current_usb_controller, 4, "usb%d", index+1);
switch (index) {
case 0:
@@ -70,8 +85,9 @@ int ehci_hcd_init(int index, enum usb_init_type init,
out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
/* Init phy */
- if (hwconfig_sub("usb1", "phy_type"))
- phy_type = hwconfig_subarg("usb1", "phy_type", &len);
+ if (hwconfig_sub(current_usb_controller, "phy_type"))
+ phy_type = hwconfig_subarg(current_usb_controller,
+ "phy_type", &len);
else
phy_type = getenv("usb_phy_type");
@@ -109,6 +125,10 @@ int ehci_hcd_init(int index, enum usb_init_type init,
in_le32(&ehci->usbmode);
+ if (SVR_SOC_VER(get_svr()) == SVR_T4240 &&
+ IS_SVR_REV(get_svr(), 2, 0))
+ set_txfifothresh(ehci, TXFIFOTHRESH);
+
return 0;
}
@@ -120,3 +140,17 @@ int ehci_hcd_stop(int index)
{
return 0;
}
+
+/*
+ * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
+ * to counter DDR latencies in writing data into Tx buffer.
+ * This prevents Tx buffer from getting underrun
+ */
+static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
+{
+ u32 cmd;
+ cmd = ehci_readl(&ehci->txfilltuning);
+ cmd &= ~TXFIFO_THRESH_MASK;
+ cmd |= TXFIFO_THRESH(txfifo_thresh);
+ ehci_writel(&ehci->txfilltuning, cmd);
+}
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 6017090..eaf5913 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -998,8 +998,8 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
if (!ehcic[index].periodic_list)
return -ENOMEM;
for (i = 0; i < 1024; i++) {
- ehcic[index].periodic_list[i] = (uint32_t)periodic
- | QH_LINK_TYPE_QH;
+ ehcic[index].periodic_list[i] = cpu_to_hc32((uint32_t)periodic
+ | QH_LINK_TYPE_QH);
}
flush_dcache_range((uint32_t)ehcic[index].periodic_list,
@@ -1089,7 +1089,7 @@ struct int_queue {
struct qTD *tds;
};
-#define NEXT_QH(qh) (struct QH *)((qh)->qh_link & ~0x1f)
+#define NEXT_QH(qh) (struct QH *)(hc32_to_cpu((qh)->qh_link) & ~0x1f)
static int
enable_periodic(struct ehci_ctrl *ctrl)
@@ -1184,41 +1184,47 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize,
struct qTD *td = result->tds + i;
void **buf = &qh->buffer;
- qh->qh_link = (uint32_t)(qh+1) | QH_LINK_TYPE_QH;
+ qh->qh_link = cpu_to_hc32((uint32_t)(qh+1) | QH_LINK_TYPE_QH);
if (i == queuesize - 1)
- qh->qh_link = QH_LINK_TERMINATE;
+ qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
- qh->qh_overlay.qt_next = (uint32_t)td;
- qh->qh_overlay.qt_altnext = QT_NEXT_TERMINATE;
- qh->qh_endpt1 = (0 << 28) | /* No NAK reload (ehci 4.9) */
+ qh->qh_overlay.qt_next = cpu_to_hc32((uint32_t)td);
+ qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
+ qh->qh_endpt1 =
+ cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */
(usb_maxpacket(dev, pipe) << 16) | /* MPS */
(1 << 14) |
QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
(usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
- (usb_pipedevice(pipe) << 0);
- qh->qh_endpt2 = (1 << 30) | /* 1 Tx per mframe */
- (1 << 0); /* S-mask: microframe 0 */
+ (usb_pipedevice(pipe) << 0));
+ qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */
+ (1 << 0)); /* S-mask: microframe 0 */
if (dev->speed == USB_SPEED_LOW ||
dev->speed == USB_SPEED_FULL) {
debug("TT: port: %d, hub address: %d\n",
dev->portnr, dev->parent->devnum);
- qh->qh_endpt2 |= (dev->portnr << 23) |
+ qh->qh_endpt2 |= cpu_to_hc32((dev->portnr << 23) |
(dev->parent->devnum << 16) |
- (0x1c << 8); /* C-mask: microframes 2-4 */
+ (0x1c << 8)); /* C-mask: microframes 2-4 */
}
- td->qt_next = QT_NEXT_TERMINATE;
- td->qt_altnext = QT_NEXT_TERMINATE;
+ td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
+ td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
debug("communication direction is '%s'\n",
usb_pipein(pipe) ? "in" : "out");
- td->qt_token = (elementsize << 16) |
+ td->qt_token = cpu_to_hc32((elementsize << 16) |
((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
- 0x80; /* active */
- td->qt_buffer[0] = (uint32_t)buffer + i * elementsize;
- td->qt_buffer[1] = (td->qt_buffer[0] + 0x1000) & ~0xfff;
- td->qt_buffer[2] = (td->qt_buffer[0] + 0x2000) & ~0xfff;
- td->qt_buffer[3] = (td->qt_buffer[0] + 0x3000) & ~0xfff;
- td->qt_buffer[4] = (td->qt_buffer[0] + 0x4000) & ~0xfff;
+ 0x80); /* active */
+ td->qt_buffer[0] =
+ cpu_to_hc32((uint32_t)buffer + i * elementsize);
+ td->qt_buffer[1] =
+ cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff);
+ td->qt_buffer[2] =
+ cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff);
+ td->qt_buffer[3] =
+ cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff);
+ td->qt_buffer[4] =
+ cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
*buf = buffer + i * elementsize;
}
@@ -1241,7 +1247,7 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize,
/* hook up to periodic list */
struct QH *list = &ctrl->periodic_queue;
result->last->qh_link = list->qh_link;
- list->qh_link = (uint32_t)result->first | QH_LINK_TYPE_QH;
+ list->qh_link = cpu_to_hc32((uint32_t)result->first | QH_LINK_TYPE_QH);
flush_dcache_range((uint32_t)result->last,
ALIGN_END_ADDR(struct QH, result->last, 1));
@@ -1280,7 +1286,7 @@ void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
/* still active */
invalidate_dcache_range((uint32_t)cur,
ALIGN_END_ADDR(struct QH, cur, 1));
- if (cur->qh_overlay.qt_token & 0x80) {
+ if (cur->qh_overlay.qt_token & cpu_to_hc32(0x80)) {
debug("Exit poll_int_queue with no completed intr transfer. "
"token is %x\n", cur->qh_overlay.qt_token);
return NULL;
@@ -1311,7 +1317,7 @@ destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
struct QH *cur = &ctrl->periodic_queue;
timeout = get_timer(0) + 500; /* abort after 500ms */
- while (!(cur->qh_link & QH_LINK_TERMINATE)) {
+ while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) {
debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
if (NEXT_QH(cur) == queue->first) {
debug("found candidate. removing from chain\n");
diff --git a/drivers/usb/host/ehci-rmobile.c b/drivers/usb/host/ehci-rmobile.c
new file mode 100644
index 0000000..049e4c4
--- /dev/null
+++ b/drivers/usb/host/ehci-rmobile.c
@@ -0,0 +1,130 @@
+/*
+ * EHCI HCD (Host Controller Driver) for USB.
+ *
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ehci-rmobile.h>
+#include "ehci.h"
+
+#if defined(CONFIG_R8A7740)
+static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
+ 0xC6700000
+};
+#elif defined(CONFIG_R8A7790)
+static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
+ 0xEE080000, /* USB0 (EHCI) */
+ 0xEE0A0000, /* USB1 */
+ 0xEE0C0000, /* USB2 */
+ 0xEE000000 /* USB3 (USB3.0 Host)*/
+};
+#elif defined(CONFIG_R8A7791)
+static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
+ 0xEE080000, /* USB0 (EHCI) */
+ 0xEE0C0000, /* USB1 */
+ 0xEE000000 /* USB3 (USB3.0 Host)*/
+};
+#else
+#error rmobile EHCI USB driver not supported on this platform
+#endif
+
+int ehci_hcd_stop(int index)
+{
+ int i;
+ u32 base;
+ struct ahbcom_pci_bridge *ahbcom_pci;
+
+ base = usb_base_address[index];
+ ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET);
+ writel(0, &ahbcom_pci->ahb_bus_ctr);
+
+ /* reset ehci */
+ setbits_le32(base + EHCI_USBCMD, CMD_RESET);
+ for (i = 100; i > 0; i--) {
+ if (!(readl(base + EHCI_USBCMD) & CMD_RESET))
+ break;
+ udelay(100);
+ }
+
+ if (!i)
+ printf("error : ehci(%d) reset failed.\n", index);
+
+ if (index == (CONFIG_USB_MAX_CONTROLLER_COUNT - 1))
+ setbits_le32(SMSTPCR7, SMSTPCR703);
+
+ return 0;
+}
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ u32 base;
+ u32 phys_base;
+ struct rmobile_ehci_reg *rehci;
+ struct ahbcom_pci_bridge *ahbcom_pci;
+ struct ahbconf_pci_bridge *ahbconf_pci;
+ struct ahb_pciconf *ahb_pciconf_ohci;
+ struct ahb_pciconf *ahb_pciconf_ehci;
+ uint32_t cap_base;
+
+ base = usb_base_address[index];
+ phys_base = base;
+ if (index == 0)
+ clrbits_le32(SMSTPCR7, SMSTPCR703);
+
+ rehci = (struct rmobile_ehci_reg *)(base + EHCI_OFFSET);
+ ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET);
+ ahbconf_pci =
+ (struct ahbconf_pci_bridge *)(base + PCI_CONF_AHBPCI_OFFSET);
+ ahb_pciconf_ohci = (struct ahb_pciconf *)(base + PCI_CONF_OHCI_OFFSET);
+ ahb_pciconf_ehci = (struct ahb_pciconf *)(base + PCI_CONF_EHCI_OFFSET);
+
+ /* Clock & Reset & Direct Power Down */
+ clrsetbits_le32(&ahbcom_pci->usbctr,
+ (DIRPD | PCICLK_MASK | USBH_RST), USBCTR_WIN_SIZE_1GB);
+ clrbits_le32(&ahbcom_pci->usbctr, PLL_RST);
+
+ /* AHB-PCI Bridge Communication Registers */
+ writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr);
+ writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH,
+ &ahbcom_pci->pciahb_win1_ctr);
+ writel(0xf0000000 | PCIAHB_WIN_PREFETCH,
+ &ahbcom_pci->pciahb_win2_ctr);
+ writel(phys_base | PCIWIN2_PCICMD, &ahbcom_pci->ahbpci_win2_ctr);
+
+ setbits_le32(&ahbcom_pci->pci_arbiter_ctr,
+ PCIBP_MODE | PCIREQ1 | PCIREQ0);
+
+ /* PCI Configuration Registers for AHBPCI */
+ writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI,
+ &ahbcom_pci->ahbpci_win1_ctr);
+ writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead);
+ writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead);
+ writel(0xf0000000, &ahbconf_pci->win2_basead);
+ writel(SERREN | PERREN | MASTEREN | MEMEN,
+ &ahbconf_pci->cmnd_sts);
+
+ /* PCI Configuration Registers for EHCI */
+ writel(PCIWIN1_PCICMD | AHB_CFG_HOST, &ahbcom_pci->ahbpci_win1_ctr);
+ writel(phys_base + OHCI_OFFSET, &ahb_pciconf_ohci->basead);
+ writel(phys_base + EHCI_OFFSET, &ahb_pciconf_ehci->basead);
+ writel(SERREN | PERREN | MASTEREN | MEMEN,
+ &ahb_pciconf_ohci->cmnd_sts);
+ writel(SERREN | PERREN | MASTEREN | MEMEN,
+ &ahb_pciconf_ehci->cmnd_sts);
+
+ /* Enable PCI interrupt */
+ setbits_le32(&ahbcom_pci->pci_int_enable,
+ USBH_PMEEN | USBH_INTBEN | USBH_INTAEN);
+
+ *hccr = (struct ehci_hccr *)((uint32_t)&rehci->hciversion);
+ cap_base = ehci_readl(&(*hccr)->cr_capbase);
+ *hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(cap_base));
+
+ return 0;
+}
diff --git a/drivers/usb/host/xhci-exynos5.c b/drivers/usb/host/xhci-exynos5.c
index 1146d10..b4946a3 100644
--- a/drivers/usb/host/xhci-exynos5.c
+++ b/drivers/usb/host/xhci-exynos5.c
@@ -298,7 +298,8 @@ int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
#ifdef CONFIG_OF_CONTROL
/* setup the Vbus gpio here */
- if (!fdtdec_setup_gpio(&ctx->vbus_gpio))
+ if (fdt_gpio_isvalid(&ctx->vbus_gpio) &&
+ !fdtdec_setup_gpio(&ctx->vbus_gpio))
gpio_direction_output(ctx->vbus_gpio.gpio, 1);
#endif
diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c
index 0512680..0d7b89f 100644
--- a/drivers/usb/musb-new/musb_uboot.c
+++ b/drivers/usb/musb-new/musb_uboot.c
@@ -204,7 +204,10 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
{
- /* TODO: implement me */
+ if (driver->disconnect)
+ driver->disconnect(&gadget->g);
+ if (driver->unbind)
+ driver->unbind(&gadget->g);
return 0;
}
#endif /* CONFIG_MUSB_GADGET */