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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-11-05 20:50:39 +0100
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-11-05 20:50:39 +0100
commitc0e5dd88c438a41bf180dde0c2dc4c67dcd8058d (patch)
treeda81a7a9b2616bfb0db1331089b390c7c92af247 /drivers
parentf6723794fd8f3362c4f3b5d0f36607a6a6f107b2 (diff)
parentc12f941bece9ed79efccfe9e4a9fd977da6975f9 (diff)
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Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master'
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/macb.c20
-rw-r--r--drivers/net/macb.h11
-rw-r--r--drivers/usb/host/ohci-at91.c19
3 files changed, 40 insertions, 10 deletions
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index bf3983a..781a272 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -621,6 +621,24 @@ static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
return config;
}
+/*
+ * Get the DMA bus width field of the network configuration register that we
+ * should program. We find the width from decoding the design configuration
+ * register to find the maximum supported data bus width.
+ */
+static u32 macb_dbw(struct macb_device *macb)
+{
+ switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
+ case 4:
+ return GEM_BF(DBW, GEM_DBW128);
+ case 2:
+ return GEM_BF(DBW, GEM_DBW64);
+ case 1:
+ default:
+ return GEM_BF(DBW, GEM_DBW32);
+ }
+}
+
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
{
struct macb_device *macb;
@@ -665,7 +683,7 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
*/
if (macb_is_gem(macb)) {
ncfgr = gem_mdc_clk_div(id, macb);
- ncfgr |= GEM_BF(DBW, 1);
+ ncfgr |= macb_dbw(macb);
} else {
ncfgr = macb_mdc_clk_div(id, macb);
}
diff --git a/drivers/net/macb.h b/drivers/net/macb.h
index de5214f..06f7c66 100644
--- a/drivers/net/macb.h
+++ b/drivers/net/macb.h
@@ -58,6 +58,9 @@
#define MACB_WOL 0x00c4
#define MACB_MID 0x00fc
+/* GEM specific register offsets */
+#define GEM_DCFG1 0x0280
+
/* Bitfields in NCR */
#define MACB_LB_OFFSET 0
#define MACB_LB_SIZE 1
@@ -242,6 +245,14 @@
#define MACB_IDNUM_SIZE 16
/* Bitfields in DCFG1 */
+#define GEM_DBWDEF_OFFSET 25
+#define GEM_DBWDEF_SIZE 3
+
+/* constants for data bus width */
+#define GEM_DBW32 0
+#define GEM_DBW64 1
+#define GEM_DBW128 2
+
/* Constants for CLK */
#define MACB_CLK_DIV8 0
#define MACB_CLK_DIV16 1
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index 9e90d59..c24505e 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -18,15 +18,15 @@ int usb_cpu_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
-#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
- defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
- defined(CONFIG_AT91SAM9261)
+#ifdef CONFIG_USB_ATMEL_CLK_SEL_PLLB
/* Enable PLLB */
writel(get_pllb_init(), &pmc->pllbr);
while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
;
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
- defined(CONFIG_AT91SAM9X5) || defined(CONFIG_SAMA5D3)
+#ifdef CONFIG_AT91SAM9N12
+ writel(AT91_PMC_USBS_USB_PLLB | AT91_PMC_USB_DIV_2, &pmc->usb);
+#endif
+#elif defined(CONFIG_USB_ATMEL_CLK_SEL_UPLL)
/* Enable UPLL */
writel(readl(&pmc->uckr) | AT91_PMC_UPLLEN | AT91_PMC_BIASEN,
&pmc->uckr);
@@ -70,14 +70,15 @@ int usb_cpu_stop(void)
writel(ATMEL_PMC_UHP, &pmc->scdr);
#endif
-#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
- defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20)
+#ifdef CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#ifdef CONFIG_AT91SAM9N12
+ writel(0, &pmc->usb);
+#endif
/* Disable PLLB */
writel(0, &pmc->pllbr);
while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0)
;
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
- defined(CONFIG_AT91SAM9X5) || defined(CONFIG_SAMA5D3)
+#elif defined(CONFIG_USB_ATMEL_CLK_SEL_UPLL)
/* Disable UPLL */
writel(readl(&pmc->uckr) & (~AT91_PMC_UPLLEN), &pmc->uckr);
while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU)