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authorWolfgang Denk <wd@denx.de>2010-03-28 00:04:18 +0100
committerWolfgang Denk <wd@denx.de>2010-03-28 00:04:18 +0100
commitbe1a91320ce0cb7330bb650d1576bb56c55092af (patch)
treef6bb6d34565d4f5b3386a23885fb3df6c17e0456 /drivers
parent6b94b4962211c16ee2197048faa887e1f92f3757 (diff)
parent9d3a86aec52cb3c0e9badd12167d9292184ce4dd (diff)
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Merge branch 'next' of git://git.denx.de/u-boot-coldfire into next
Diffstat (limited to 'drivers')
-rw-r--r--drivers/fpga/spartan3.c54
-rw-r--r--drivers/serial/mcfuart.c4
2 files changed, 31 insertions, 27 deletions
diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c
index 0fe3041..7a89b56 100644
--- a/drivers/fpga/spartan3.c
+++ b/drivers/fpga/spartan3.c
@@ -385,34 +385,38 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
} while ((*fn->init) (cookie));
/* Load the data */
- while (bytecount < bsize) {
-
- /* Xilinx detects an error if INIT goes low (active)
- while DONE is low (inactive) */
- if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
- puts ("** CRC error during FPGA load.\n");
- return (FPGA_FAIL);
- }
- val = data [bytecount ++];
- i = 8;
- do {
- /* Deassert the clock */
- (*fn->clk) (FALSE, TRUE, cookie);
- CONFIG_FPGA_DELAY ();
- /* Write data */
- (*fn->wr) ((val & 0x80), TRUE, cookie);
- CONFIG_FPGA_DELAY ();
- /* Assert the clock */
- (*fn->clk) (TRUE, TRUE, cookie);
- CONFIG_FPGA_DELAY ();
- val <<= 1;
- i --;
- } while (i > 0);
+ if(*fn->bwr)
+ (*fn->bwr) (data, bsize, TRUE, cookie);
+ else {
+ while (bytecount < bsize) {
+
+ /* Xilinx detects an error if INIT goes low (active)
+ while DONE is low (inactive) */
+ if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
+ puts ("** CRC error during FPGA load.\n");
+ return (FPGA_FAIL);
+ }
+ val = data [bytecount ++];
+ i = 8;
+ do {
+ /* Deassert the clock */
+ (*fn->clk) (FALSE, TRUE, cookie);
+ CONFIG_FPGA_DELAY ();
+ /* Write data */
+ (*fn->wr) ((val & 0x80), TRUE, cookie);
+ CONFIG_FPGA_DELAY ();
+ /* Assert the clock */
+ (*fn->clk) (TRUE, TRUE, cookie);
+ CONFIG_FPGA_DELAY ();
+ val <<= 1;
+ i --;
+ } while (i > 0);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- if (bytecount % (bsize / 40) == 0)
- putc ('.'); /* let them know we are alive */
+ if (bytecount % (bsize / 40) == 0)
+ putc ('.'); /* let them know we are alive */
#endif
+ }
}
CONFIG_FPGA_DELAY ();
diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c
index 0b53140..d93b24b 100644
--- a/drivers/serial/mcfuart.c
+++ b/drivers/serial/mcfuart.c
@@ -34,7 +34,7 @@
DECLARE_GLOBAL_DATA_PTR;
-extern void uart_port_conf(void);
+extern void uart_port_conf(int port);
int serial_init(void)
{
@@ -43,7 +43,7 @@ int serial_init(void)
uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
- uart_port_conf();
+ uart_port_conf(CONFIG_SYS_UART_PORT);
/* write to SICR: SIM2 = uart mode,dcd does not affect rx */
uart->ucr = UART_UCR_RESET_RX;