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authorSoren Brinkmann <soren.brinkmann@xilinx.com>2013-11-21 13:39:01 -0800
committerMichal Simek <michal.simek@xilinx.com>2014-02-19 09:41:21 +0100
commit97598fcf10eba577622f3387eaecd43dd710da0d (patch)
tree68f59303d1d8f6ca2d941f8365fa00868091603e /drivers
parent1cd46ed2d30a931a66400635f158b14861f2d3b4 (diff)
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net: zynq_gem: Calculate clock dividers dynamically
Remove hard coded clock divider setting and use the Zynq clock framework to dynamically calculate appropriate dividers at run time. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/zynq_gem.c17
1 files changed, 11 insertions, 6 deletions
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 2eb9e7d..6d4001b 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -90,6 +90,11 @@
#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
+/* Clock frequencies for different speeds */
+#define ZYNQ_GEM_FREQUENCY_10 2500000UL
+#define ZYNQ_GEM_FREQUENCY_100 25000000UL
+#define ZYNQ_GEM_FREQUENCY_1000 125000000UL
+
/* Device registers */
struct zynq_gem_regs {
u32 nwctrl; /* Network Control reg */
@@ -270,7 +275,8 @@ static int zynq_gem_setup_mac(struct eth_device *dev)
static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
{
- u32 i, clk = 0;
+ u32 i;
+ unsigned long clk_rate = 0;
struct phy_device *phydev;
const u32 stat_size = (sizeof(struct zynq_gem_regs) -
offsetof(struct zynq_gem_regs, stat)) / 4;
@@ -348,23 +354,22 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
case SPEED_1000:
writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
&regs->nwcfg);
- clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
+ clk_rate = ZYNQ_GEM_FREQUENCY_1000;
break;
case SPEED_100:
clrsetbits_le32(&regs->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
- clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
+ clk_rate = ZYNQ_GEM_FREQUENCY_100;
break;
case SPEED_10:
- /* FIXME untested */
- clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
+ clk_rate = ZYNQ_GEM_FREQUENCY_10;
break;
}
/* Change the rclk and clk only not using EMIO interface */
if (!priv->emio)
zynq_slcr_gem_clk_setup(dev->iobase !=
- ZYNQ_GEM_BASEADDR0, clk);
+ ZYNQ_GEM_BASEADDR0, clk_rate);
setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK);