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| author | Peng Fan <Peng.Fan@freescale.com> | 2015-11-26 14:19:44 +0800 |
|---|---|---|
| committer | Peng Fan <Peng.Fan@freescale.com> | 2015-11-27 09:54:08 +0800 |
| commit | 6cdc3c37b96de9e9f42b79ccfeceda50518a9344 (patch) | |
| tree | 1995b35fcc73d3c50a320d5a95ef2676a13aed6b /drivers | |
| parent | e3618dfec24f62671685f834c14b12d9fd5e944a (diff) | |
| download | u-boot-imx-6cdc3c37b96de9e9f42b79ccfeceda50518a9344.zip u-boot-imx-6cdc3c37b96de9e9f42b79ccfeceda50518a9344.tar.gz u-boot-imx-6cdc3c37b96de9e9f42b79ccfeceda50518a9344.tar.bz2 | |
MLK-11897 video: ipu: fix out of bounds access
We need to access reg stp_rep9, but not stp_rep[(9 - 1) / 2].
If using "__raw_writel(0, DI_STP_REP(disp, 9))", this will exceeds
the size of stp_rep array.
Acked-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/video/ipu_disp.c | 2 | ||||
| -rw-r--r-- | drivers/video/ipu_regs.h | 3 |
2 files changed, 3 insertions, 2 deletions
diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c index 5a8727f..e872500 100644 --- a/drivers/video/ipu_disp.c +++ b/drivers/video/ipu_disp.c @@ -1129,7 +1129,7 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, reg &= 0x0000FFFF; __raw_writel(reg, DI_STP_REP(disp, 6)); __raw_writel(0, DI_STP_REP(disp, 7)); - __raw_writel(0, DI_STP_REP(disp, 9)); + __raw_writel(0, DI_STP_REP9(disp)); /* Init template microcode */ if (disp) { diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h index f800405..4cad1bd 100644 --- a/drivers/video/ipu_regs.h +++ b/drivers/video/ipu_regs.h @@ -6,7 +6,7 @@ * * Linux IPU driver for MX51: * - * (C) Copyright 2005-2014 Freescale Semiconductor, Inc. + * (C) Copyright 2005-2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -338,6 +338,7 @@ struct ipu_dmfc { #define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[gen - 1]) #define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[gen - 1]) #define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[(gen - 1) / 2]) +#define DI_STP_REP9(di) (&DI_REG(di)->stp_rep9) #define DI_SYNC_AS_GEN(di) (&DI_REG(di)->sync_as) #define DI_DW_GEN(di, gen) (&DI_REG(di)->dw_gen[gen]) #define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[gen + 12 * set]) |