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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-02-19 10:55:58 +0100
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-02-19 10:55:58 +0100
commit1feb6e3c9216a34885f24f0df4a02a30dfb35f19 (patch)
treea971d9d2fe6528910cf7acaf7632b747731c6caa /drivers
parent529a8d05ff848e7bfd6049c99210557aa5e31d39 (diff)
parente158665c1e4c4665302f0d95e26b7c7e6b70a83c (diff)
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Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/zynq_gem.c20
-rw-r--r--drivers/serial/serial_zynq.c33
2 files changed, 26 insertions, 27 deletions
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 381bca4..6d4001b 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -90,6 +90,11 @@
#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
+/* Clock frequencies for different speeds */
+#define ZYNQ_GEM_FREQUENCY_10 2500000UL
+#define ZYNQ_GEM_FREQUENCY_100 25000000UL
+#define ZYNQ_GEM_FREQUENCY_1000 125000000UL
+
/* Device registers */
struct zynq_gem_regs {
u32 nwctrl; /* Network Control reg */
@@ -270,7 +275,8 @@ static int zynq_gem_setup_mac(struct eth_device *dev)
static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
{
- u32 i, rclk, clk = 0;
+ u32 i;
+ unsigned long clk_rate = 0;
struct phy_device *phydev;
const u32 stat_size = (sizeof(struct zynq_gem_regs) -
offsetof(struct zynq_gem_regs, stat)) / 4;
@@ -348,26 +354,22 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
case SPEED_1000:
writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
&regs->nwcfg);
- rclk = (0 << 4) | (1 << 0);
- clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
+ clk_rate = ZYNQ_GEM_FREQUENCY_1000;
break;
case SPEED_100:
clrsetbits_le32(&regs->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
- rclk = 1 << 0;
- clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
+ clk_rate = ZYNQ_GEM_FREQUENCY_100;
break;
case SPEED_10:
- rclk = 1 << 0;
- /* FIXME untested */
- clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
+ clk_rate = ZYNQ_GEM_FREQUENCY_10;
break;
}
/* Change the rclk and clk only not using EMIO interface */
if (!priv->emio)
zynq_slcr_gem_clk_setup(dev->iobase !=
- ZYNQ_GEM_BASEADDR0, rclk, clk);
+ ZYNQ_GEM_BASEADDR0, clk_rate);
setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK);
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index ff28f3c..22c6bf0 100644
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -10,6 +10,8 @@
#include <asm/io.h>
#include <linux/compiler.h>
#include <serial.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/hardware.h>
#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
@@ -33,28 +35,24 @@ struct uart_zynq {
};
static struct uart_zynq *uart_zynq_ports[2] = {
-#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
- [0] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR0,
+ [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0,
+ [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1,
+};
+
+#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0)
+# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE
#endif
-#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
- [1] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR1,
+#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1)
+# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE
#endif
-};
struct uart_zynq_params {
u32 baudrate;
- u32 clock;
};
static struct uart_zynq_params uart_zynq_ports_param[2] = {
-#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) && defined(CONFIG_ZYNQ_SERIAL_CLOCK0)
[0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0,
- [0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0,
-#endif
-#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) && defined(CONFIG_ZYNQ_SERIAL_CLOCK1)
[1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1,
- [1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1,
-#endif
};
/* Set up the baud rate in gd struct */
@@ -64,7 +62,7 @@ static void uart_zynq_serial_setbrg(const int port)
unsigned int calc_bauderror, bdiv, bgen;
unsigned long calc_baud = 0;
unsigned long baud = uart_zynq_ports_param[port].baudrate;
- unsigned long clock = uart_zynq_ports_param[port].clock;
+ unsigned long clock = get_uart_clk(port);
struct uart_zynq *regs = uart_zynq_ports[port];
/* master clock
@@ -186,20 +184,19 @@ struct serial_device uart_zynq_serial1_device =
__weak struct serial_device *default_serial_console(void)
{
+#if defined(CONFIG_ZYNQ_SERIAL_UART0)
if (uart_zynq_ports[0])
return &uart_zynq_serial0_device;
+#endif
+#if defined(CONFIG_ZYNQ_SERIAL_UART1)
if (uart_zynq_ports[1])
return &uart_zynq_serial1_device;
-
+#endif
return NULL;
}
void zynq_serial_initalize(void)
{
-#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
serial_register(&uart_zynq_serial0_device);
-#endif
-#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
serial_register(&uart_zynq_serial1_device);
-#endif
}