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| author | Marek Vasut <marex@denx.de> | 2015-07-12 23:14:33 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-08-08 14:14:12 +0200 |
| commit | 162d60ef733a1878eee85cf1f3ed5e56f2a26903 (patch) | |
| tree | dbe33629c1c5abe71ddda7c83193113c14c7157e /drivers | |
| parent | e893f4dc2fb3a837b765c61692ca174fca611d53 (diff) | |
| download | u-boot-imx-162d60ef733a1878eee85cf1f3ed5e56f2a26903.zip u-boot-imx-162d60ef733a1878eee85cf1f3ed5e56f2a26903.tar.gz u-boot-imx-162d60ef733a1878eee85cf1f3ed5e56f2a26903.tar.bz2 | |
ddr: altera: Shuffle around scc_mgr_set_*all_ranks()
Shuffle the code around a bit, but without any functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ddr/altera/sequencer.c | 19 |
1 files changed, 8 insertions, 11 deletions
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 4bdc3a7..1718ebf 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -365,10 +365,11 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group, uint32_t phase) { uint32_t r; - uint32_t update_scan_chains; for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) { + scc_mgr_set_dqs_en_phase(read_group, phase); + /* * USER although the h/w doesn't support different phases per * shadow register, for simplicity our scc manager modeling @@ -377,11 +378,8 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group, * for efficiency, the scan chain update should occur only * once to sr0. */ - update_scan_chains = (r == 0) ? 1 : 0; - - scc_mgr_set_dqs_en_phase(read_group, phase); - if (update_scan_chains) { + if (r == 0) { writel(read_group, &sdr_scc_mgr->dqs_ena); writel(0, &sdr_scc_mgr->update); } @@ -392,10 +390,11 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group, uint32_t phase) { uint32_t r; - uint32_t update_scan_chains; for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) { + scc_mgr_set_dqdqs_output_phase(write_group, phase); + /* * USER although the h/w doesn't support different phases per * shadow register, for simplicity our scc manager modeling @@ -404,11 +403,8 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group, * for efficiency, the scan chain update should occur only * once to sr0. */ - update_scan_chains = (r == 0) ? 1 : 0; - scc_mgr_set_dqdqs_output_phase(write_group, phase); - - if (update_scan_chains) { + if (r == 0) { writel(write_group, &sdr_scc_mgr->dqs_ena); writel(0, &sdr_scc_mgr->update); } @@ -424,7 +420,6 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group, r += NUM_RANKS_PER_SHADOW_REG) { scc_mgr_set_dqs_en_delay(read_group, delay); - writel(read_group, &sdr_scc_mgr->dqs_ena); /* * In shadow register mode, the T11 settings are stored in * registers in the core, which are updated by the DQS_ENA @@ -433,6 +428,8 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group, * select_shadow_regs_for_update with update_scan_chains * set to 0. */ + + writel(read_group, &sdr_scc_mgr->dqs_ena); writel(0, &sdr_scc_mgr->update); } /* |