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author | Siarhei Siamashka <siarhei.siamashka@gmail.com> | 2015-01-19 05:23:35 +0200 |
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committer | Hans de Goede <hdegoede@redhat.com> | 2015-01-22 12:34:56 +0100 |
commit | dddccd6913142e0ba63ce6e529c38651c2ab0197 (patch) | |
tree | e1819e3251f887c0e2724be99b82f75512706ece /drivers/video/mb86r0xgdc.c | |
parent | aaa6ac5eab8df95a3b9646194d90f49e79476258 (diff) | |
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video: ssd2828: Allow using 'pclk' as the PLL clock source
Instead of using the internal 'tx_clk' clock source, it is also
possible to use the pixel clock signal from the parallel LCD
interface ('pclk') as the reference clock for PLL.
The 'tx_clk' clock speed may be different on different boards/devices
(the allowed range is 8MHz - 30MHz). Which is not very convenient,
especially considering the need to know the exact 'tx_clk' clock
speed. This clock speed may be difficult to identify without having
device schematics and/or accurate documentation/sources every time.
Using 'pclk' is free from all these problems.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'drivers/video/mb86r0xgdc.c')
0 files changed, 0 insertions, 0 deletions