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authorNikhil Badola <nikhil.badola@freescale.com>2015-06-23 09:17:49 +0530
committerMarek Vasut <marex@denx.de>2015-07-22 08:55:45 +0200
commit667f4dd90f0f40f8d4fde7ef280550ef5f7946f8 (patch)
treea1aa1a10e681322ca31a4671cd3c9400cba27b8a /drivers/usb
parent7e5a32fcf378d30cb2ab5f8471071350574ff70a (diff)
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drivers: usb: fsl: Implement Erratum A-009116 for XHCI controller
This adjusts (micro)frame length to appropriate value thus avoiding USB devices to time out over a longer run Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Diffstat (limited to 'drivers/usb')
-rw-r--r--drivers/usb/host/xhci-dwc3.c6
-rw-r--r--drivers/usb/host/xhci-fsl.c3
2 files changed, 9 insertions, 0 deletions
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index 67147cb..c722c50 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -89,3 +89,9 @@ int dwc3_core_init(struct dwc3 *dwc3_reg)
return 0;
}
+
+void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
+{
+ setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
+ GFLADJ_30MHZ(val));
+}
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index 385422a..6781b94 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -58,6 +58,9 @@ static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
/* We are hard-coding DWC3 core to Host Mode */
dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+ /* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
+ dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
+
return ret;
}